T5743P3-TGQ Atmel, T5743P3-TGQ Datasheet - Page 20

• Manufacturer Part Number: T5743P3-TGQ
• Description: IC RCVR ASK/FSK 300MHZ 20-SOIC
• Manufacturer: Atmel

Specifications of T5743P3-TGQ

• Frequency: 300MHz ~ 450MHz
• Sensitivity: -108dBm
• Data Rate - Maximum: 10 kBaud
• Modulation Or Protocol: ASK, FSK
• Applications: General Purpose Data Transmission Systems
• Current - Receiving: 30mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Memory Size: -
• Other names: T5743P3-TGQTR

Figure 24. Data Clock Disappears Because of a Logical Error
Figure 25. Output of the Data Clock After a Successful Bit Check
20
T5743
DATA_CLK
Dem_out
Data_out (DATA)
Dem_out
Data_out (DATA)
DATA_CLK
The delay of the data clock is calculated as follows:
t
t
edge, t
resistor R
(see Figure 26, Figure 27 and Figure 34). When the level of Data_In is equal to the level
of Data_Out, the data clock is issued after an additional delay t
Note that the capacitive load at Pin DATA is limited. If the maximum tolerated capacitive
load at Pin DATA is exceeded, the data clock disappears (see section “Data Interface”).
Delay
Delay1
'1'
'1'
Receiving mode,
bit check active
Bit check ok
= t
is the delay between the internal signals Data_Out and Data_In. For the rising
Delay1
'1'
'1'
Delay1
pup
. For the falling edge, t
Receiving mode,
data clock control
logic active
depends on the capacitive load C
+ t
'1'
'1'
Delay2
'0'
'1'
'1'
'1'
Data
Start bit
Data
'1'
'0'
Logical error (Manchester code violation)
Delay1
Receiving mode,
data clock control
logic active
'?'
'1'
depends additionally on the external voltage V
'0'
'1'
L
at Pin DATA and the external pull-up
'0'
Receiving mode,
bit check aktive
'0'
'1'
'1'
Delay2
'0'
'0'
.
4569A–RKE–12/02
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