ATA3741P2-TGQY Atmel, ATA3741P2-TGQY Datasheet - Page 12

• Manufacturer Part Number: ATA3741P2-TGQY
• Description: IC UHF ASK/FSK RECEIVER 20SOIC
• Manufacturer: Atmel

Specifications of ATA3741P2-TGQY

• Frequency: 300MHz ~ 450MHz
• Sensitivity: -108dBm
• Data Rate - Maximum: 10 kBaud
• Modulation Or Protocol: ASK, FSK
• Applications: RKE, TPM, Security Systems
• Current - Receiving: 7mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Other names: ATA3741P2-TGQYTR

Figure 5-2.
Figure 5-3.
12
ATA3741
Polling Mode Flow Chart
Timing Diagram for a Completely Successful Bit Check
NO
Number of Checked Bits: 3
Bit check
Dem_out
DATA
Enable IC
Sleep Mode:
All circuits for signal processing are
disabled. Only XTO and polling logic is
enabled.
Output level on pin IC_ACTIVE => low
I
T
Start-up Mode:
The signal processing circuits are
enabled. After the start-up time (T
all circuits are in stable condition and
ready to receive.
I
T
Bit-check Mode:
The incoming data stream is analyzed.
If the timing indicates a valid transmitter
signal, the receiver is set to receiving
mode. Otherwise is set to Sleep mode.
I
T
Receiving Mode:
The receiver is turned on permanently
and passes the data stream to the
connected microcontroller. It can be set
to Sleep mode through an OFF command
via pin DATA or ENABLE
I
S
S
S
S
Sleep
Startup
Bitcheck
= I
= I
= I
= I
SON
SON
Son
SON
= Sleep
Polling mode
OFF command
Bit-check
X
Sleep
OK?
YES
1024
T
1/2 Bit
Clk
Startup
)
1/2 Bit
1/2 Bit
Bit check ok
Sleep:
X
T
T
T
1/2 Bit
Clk
Startup
Bitcheck
Sleep
:
:
:
:
1/2 Bit
Basic clock cycle defined by f
MODE
Is defined by the selected baud rate range
and T
by Baud0 and Baud1 in the OPMODE
register.
If the bit check is ok, T
on the number of bits to be checked
(N
5-bit word defined by Sleep0 to Sleep4 in
OPMODE register
Extension factor defined by X
according to Table 5-7
Depends on the result of the bit check.
If the bit check fails, the average time
period for that check depends on the
selected baud rate range on T
baud rate range is defined by Baud0 and
Baud1 in the OPMODE register.
Bitchecked
1/2 Bit
Clk
. The baud rate range is defined
) and on the utilized data rate.
Receiving mode
Bitcheck
XTO
depends
SleepTemp
Clk
. The
and pin
4899B–RKE–10/06