ATA3741P2-TGQY Atmel, ATA3741P2-TGQY Datasheet - Page 14

• Manufacturer Part Number: ATA3741P2-TGQY
• Description: IC UHF ASK/FSK RECEIVER 20SOIC
• Manufacturer: Atmel

Specifications of ATA3741P2-TGQY

• Frequency: 300MHz ~ 450MHz
• Sensitivity: -108dBm
• Data Rate - Maximum: 10 kBaud
• Modulation Or Protocol: ASK, FSK
• Applications: RKE, TPM, Security Systems
• Current - Receiving: 7mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Other names: ATA3741P2-TGQYTR

Figure 5-5.
Figure 5-6.
Figure 5-7.
14
ATA3741
(Lim_min = 14, Lim_max = 24)
Enable IC
Enable IC
Bit check
Dem_out
Bit check
counter
(Lim_min = 14, Lim_max = 24)
Bit check
Dem_out
Bit check
counter
(Lim_min = 14, Lim_max = 24)
Enable IC
Timing Diagram During Bit Check
Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min)
Bit check
Dem_out
Timing Diagram for Failed Bit Check (Condition: CV_Lim
Bit check
counter
Figure
Lim_min = 14 and Lim_max = 24. When the IC is enabled, the signal processing circuits are
enabled during T
that period. When the bit check becomes active, the bit-check counter is clocked with the cycle
T
Figure 5-5
limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In
check fails as the value CV_lim is lower than the limit Lim_min. The bit check also fails if CV_Lim
reaches Lim_max. This is illustrated in
Startup Mode
Startup Mode
XClk
T
Startup
0
0
0
.
5-5,
shows how the bit check proceeds if the bit-check counter value CV_Lim is within the
1
1
1
Figure 5-6
2 3 4 5 6
2 3 4 5 6
2 3 4 5 6
Startup
T
XClk
7
7 8 1
1
1
. The output of the ASK/FSK demodulator (Dem_out) is undefined during
2
Bit check Mode
2
and
3
3
2
4 5
4 5
3
1/2 Bit
Bit check Mode
Figure 5-7
4 5
6 7 8 9
6 7 8 9
6 7 8 9
Bit check failed ( CV_Lim < Lim_min )
1/2 Bit
10
10
11 12
1112
10
1/2 Bit
Figure
11121314
illustrate the bit check for the default bit-check limits
13141516171819
15161718 1 2 3 4 5 6
5-7.
Lim_max)
Bit check ok
Sleep Mode
Bit check failed (CV_Lim = Lim_max)
0
20
21222324
7 8 9 10 1112131415 1 2 3 4
1/2 Bit
Sleep Mode
0
Bit check ok
1/2 Bit
Figure
4899B–RKE–10/06
5-6, the bit