SI4330-B1-FM Silicon Laboratories Inc, SI4330-B1-FM Datasheet - Page 16
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SI4330-B1-FM
Manufacturer Part Number
SI4330-B1-FM
Description
IC RCVR ISM 960MHZ 3.6V 20-QFN
Manufacturer
Silicon Laboratories Inc
Type
ISM Receiverr
Specifications of SI4330-B1-FM
Package / Case
20-QFN
Frequency
960MHz
Sensitivity
-118dBm
Data Rate - Maximum
128kbps
Modulation Or Protocol
FSK, GFSK, OOK
Current - Receiving
18.5mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Voltage - Supply
1.8 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Operating Frequency
240 MHz to 960 MHz
Operating Supply Voltage
3 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Current
18.5 mA
Package
20QFN EP
Maximum Data Rate
256 Kbps
Transmission Media Type
Wireless
Power Supply Type
Analog
Typical Operating Supply Voltage
3 V
Minimum Operating Supply Voltage
1.8 V
Maximum Operating Supply Voltage
3.6 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Applications
-
Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1629-5
SI4330-V2-FM
SI4330-V2-FM
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SI4330-B1-FM
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Company:
Part Number:
SI4330-B1-FM-02T
Manufacturer:
SILICON
Quantity:
112
Company:
Part Number:
SI4330-B1-FMR
Manufacturer:
HIROSE
Quantity:
3 200
Part Number:
SI4330-B1-FMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Si4330-B1
3. Controller Interface
3.1. Serial Peripheral Interface (SPI)
The Si4330 communicates with the host MCU over a standard 3-wire SPI interface: SCLK, SDI, and nSEL. The
host MCU can read data from the device on the SDO output pin. A SPI transaction is a 16-bit sequence which
consists of a Read-Write (R/W) select bit, followed by a 7-bit address field (ADDR), and an 8-bit data field (DATA)
as demonstrated in Figure 2. The 7-bit address field is used to select one of the 128, 8-bit control registers. The
R/W select bit determines whether the SPI transaction is a read or write transaction. If R/W = 1 it signifies a WRITE
transaction, while R/W = 0 signifies a READ transaction. The contents (ADDR or DATA) are latched into the Si4330
every eight clock cycles. The timing parameters for the SPI interface are shown in Table 9. The SCLK rate is
flexible with a maximum rate of 10 MHz.
To read back data from the Si4330, the R/W bit must be set to 0 followed by the 7-bit address of the register from
which to read. The 8 bit DATA field following the 7-bit ADDR field is ignored n the SDI pin when R/W = 0. The next
eight negative edge transitions of the SCLK signal will clock out the contents of the selected register. The data read
from the selected register will be available on the SDO output pin. The READ function is shown in Figure 3. After
the READ function is completed the SDO pin will remain at either a logic 1 or logic 0 state depending on the last
data bit clocked out (D0). When nSEL goes high the SDO output pin will be pulled high by internal pullup.
16
Symbol
t
t
t
t
t
t
t
t
t
t
SW
CH
DS
DH
DD
EN
DE
SH
CL
SS
SCLK
nSEL
Output data delay time
Output disable time
Output enable time
Select high period
Select setup time
SDI
Select hold time
Data setup time
Clock high time
Clock low time
Data hold time
Parameter
MSB
RW
A6 A5
Table 9. Serial Interface Timing Parameters
Min (nsec)
A4
Address
50
80
40
40
20
20
20
20
50
20
A3
Figure 2. SPI Timing
A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
SDI
Rev 1.0
SCLK
SDO
nSEL
t
t
EN
SS
Data
t
CL
t
CH
Diagram
t
DS
t
DH
LSB
t
DD
xx xx
t
SH
RW A7
t
DE
t
SW