TEA5764UK-G ST-Ericsson Inc, TEA5764UK-G Datasheet - Page 18

• Manufacturer Part Number: TEA5764UK-G
• Description: IC FM STEREO RADIO W/RDS 34WLB
• Manufacturer: ST-Ericsson Inc

Specifications of TEA5764UK-G

• Frequency: 76MHz ~ 90MHz, 87.5MHz ~ 108MHz
• Sensitivity: -108dBm
• Modulation Or Protocol: FM
• Applications: FM Radio Receiver
• Current - Receiving: 1.5mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 2.5 V ~ 3.3 V
• Package / Case: 34-WLBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Operating Temperature: -
• Memory Size: -
• Data Rate - Maximum: -
• Other names: 935278071027

Philips Semiconductors
TEA5764UK_2
Product data sheet
9.1.1 Interrupt clearing
9.1.2 Timing
9.1.3 Reset
The interrupt flag register contains the flags set according to the behavior outlined in
Section
(hardware interrupt line) depending on the status of the corresponding mask bit in
A logic 1 in the mask register enables the hardware interrupt for that flag.
Hence, it is conceivable that, with all the mask bits cleared, the software could operate in
a continuous polling mode that reads the interrupt flag register for any bits that maybe set.
Interrupt mask bits are always cleared after reading the first two bytes of the interrupt
register. This is to control multiple hardware interrupts (see
a different function and is not cleared after reading the interrupt register bytes, see also
Section
The interrupt flag and mask bits are always cleared after:
The timing sequence for the general operation interrupts is shown in
a read access of the interrupt bytes INTFLAG and INTMSK and a subsequent (though not
necessarily immediate) write to the mask register. It also indicates the two key timing
points A and B.
If an interrupt event occurs while the register is being accessed (after point A) it must be
held until after the mask register is cleared at the end of the read operation (point B).
Point A is after the R/W bit has been decoded and point B is where the acknowledge has
been received from the master after the first two bytes have been sent.
The LOW time for the INTX line (t
However it can be shorter if the read of the INTMSK and INTFLAG bytes occurs within
t
A reset can be performed at any time by a simple read of the interrupt bytes, byte0R and
byte0W, which automatically clears the interrupt flags and masks.
LOW
•
•
They have been read via the I
A power-on reset
.
9.1.4. When these flags are set they can also cause the INTX to go active
9.1.4.3.
Rev. 02 — 9 August 2005
LOW
2
C-bus
) has a maximum value specified in
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Figure
TEA5764UK
6). Bit LSYNCMSK has
Figure 6
FM radio + RDS
Section
and shows
Table
14.
17 of 64
7.