TEA5764UK-G ST-Ericsson Inc, TEA5764UK-G Datasheet - Page 20

• Manufacturer Part Number: TEA5764UK-G
• Description: IC FM STEREO RADIO W/RDS 34WLB
• Manufacturer: ST-Ericsson Inc

Specifications of TEA5764UK-G

• Frequency: 76MHz ~ 90MHz, 87.5MHz ~ 108MHz
• Sensitivity: -108dBm
• Modulation Or Protocol: FM
• Applications: FM Radio Receiver
• Current - Receiving: 1.5mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 2.5 V ~ 3.3 V
• Package / Case: 34-WLBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Operating Temperature: -
• Memory Size: -
• Data Rate - Maximum: -
• Other names: 935278071027

Philips Semiconductors
TEA5764UK_2
Product data sheet
9.1.4.1 Multiple interrupt events
9.1.4.2 Data available flag
9.1.4.3 RDS synchronization flag
9.1.4 Interrupt flags and behavior
If the interrupt mask register bit is set then the setting of an interrupt flag for that bit
causes a hardware interrupt (pin INTX goes LOW). If the event occurs again, before the
flag is cleared, then this does not trigger any further hardware interrupts until that specific
flag is cleared. However, two different events can occur in sequence and generate a
sequence of hardware interrupts. A second interrupt can be generated only after the
INTMSK byte is read, followed by a write as the first interrupt blocks the input of the INTX
one-shot generator.
If subsequent interrupts occur within the INTX LOW period then these do not cause the
INTX period to extend beyond its specified maximum period (see
The DAVFLG is set when a new block of data is received according to the diagrams
shown in
this continues for all subsequent received blocks (dependent on DAV mode) and in the
following situations:
The DAVFLG is reset by a read of RDSLBLSB (byte15R) or RDSPBLSB (byte17R). An
interrupt is asserted each time a new block of data is decoded and when bit DAVMSK is
set; for details see
Bit SYNC,
decoder is synchronized, if it is a logic 0 it is not.
The action of the TEA5764UK depends on the status of bit LSYNCMSK in
is set then the loss of synchronization causes bit LSYNCFL to go to logic 1 when
synchronization is lost, and a hardware interrupt is asserted. The RDS part of the
TEA5764UK is set to idle and waits for the microprocessor to initiate a new
synchronization search by setting bit NWSY as described in
•
•
•
•
•
During sync search, in any DAV mode: two valid blocks in the correct sequence
received with BBC < BBL (synchronized).
During synchronization search in DAVB mode if a valid A(C’)-block has been
detected. This mode can be used for fast search tuning (detection and comparison of
the PI code contained in the A or C’ block.
If the pre-processor is synchronized and in mode DAVA and DAVB a new block has
been processed. This mode is the standard data processing mode if the decoder is
synchronized.
If the pre-processor is synchronized and in DAVC mode, two new blocks have been
processed.
If the decoder is synchronized and in any DAV mode, with LSYNCMSK = 0, loss of
synchronization is detected (flywheel loss of synchronization, resulting in a restart of
synchronization search).
Section 10
Table
29, shows the status of the RDS decoder. If it is a logic 1 then the
Section
where the different DAV modes are described. Once synchronized,
Rev. 02 — 9 August 2005
10.
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Table
TEA5764UK
Section
36.
FM radio + RDS
9.2).
Table
7. If this
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