ATA5824-PLQW Atmel, ATA5824-PLQW Datasheet - Page 70

• Manufacturer Part Number: ATA5824-PLQW
• Description: IC TXRX UHF ASK/FSK 48QFN
• Manufacturer: Atmel

Specifications of ATA5824-PLQW

• Frequency: 433 ~ 435MHz; 866 ~ 870MHz
• Data Rate - Maximum: 20kbps
• Modulation Or Protocol: ASK, FSK
• Applications: RKE, TPM, Security Systems
• Power - Output: 10dBm
• Sensitivity: -116dBm
• Voltage - Supply: 2.15 V ~ 3.6 V or 4.4 V ~ 5.25 V
• Current - Receiving: 10.5mA
• Current - Transmitting: 10.5mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -

14.4
70
Interrupts
ATA5823/ATA5824
Via pin IRQ, the transceiver signals different operating conditions to a connected microcon-
troller. If a specific operating condition occurs, pin IRQ is set to a high level.
If an interrupt occurs, it is recommended to delete the interrupt immediately by reading the sta-
tus register, thus the next possible interrupt doesn’t get lost. If the Interrupt pin doesn’t switch to
a low level by reading the status register, the interrupt was triggered by the RX/TX data buffer. In
this case, read or write the RX/TX data buffer according to
Table 14-8.
Events in Status Register
State transition of status bit N_Power_On
(0
Appearance of status bit Power_On
(0
Events During TX Operation (T_MODE = 0)
1, 2, 4 or 12 bytes are in the TX data buffer or
the TX data buffer is empty (depends on IR0
and IR1 in control register 1)
Events During RX Operation (T_MODE = 0)
1, 2, 4 or 12 received bytes are in the RX data
buffer or a receiving error is occurred (depends
on IR0 and IR1 in control register 1)
Successful Bit-check (P_MODE = 0)
Events During FD Operation
TX data buffer empty
Note:
Operating Conditions Which Sets Pin IRQ
1; 1
1)
1. During reading of the RX/TX buffer, no IRQ is issued, due to the received bytes or a receiv-
ing error.
0)
Interrupt Handling
to High Level
Read status register or
Command delete IRQ
Write TX data buffer or
Write control register 1 or
Write control register 4 or
Write control register 5 or
Write control register 6 or
Write control register 7 or
Command delete IRQ
Read RX data buffer
Write control register 1 or
Write control register 4 or
Write control register 5 or
Write control register 6 or
Write control register 7 or
Command delete IRQ
Read RX data buffer
Write control register 1 or
Write control register 4 or
Write control register 5 or
Write control register 6 or
Write control register 7 or
Command delete IRQ
Operations Which Sets Pin IRQ to Low Level
Table
(1)
(1)
14-8.
or
or
4829D–RKE–06/06