ATMEGA128RZAV-8MU Atmel, ATMEGA128RZAV-8MU Datasheet - Page 81
ATMEGA128RZAV-8MU
Manufacturer Part Number
ATMEGA128RZAV-8MU
Description
MCU ATMEGA1281/AT86RF230 64-QFN
Manufacturer
Atmel
Series
ATMEGAr
Datasheets
1.ATMEGA640V-8CU.pdf
(38 pages)
2.ATMEGA640V-8CU.pdf
(444 pages)
3.AT86RF230-ZU.pdf
(98 pages)
Specifications of ATMEGA128RZAV-8MU
Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3dBm
Sensitivity
-101dBm
Voltage - Supply
1.8 V ~ 3.6 V
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 8kB RAM
Antenna Connector
PCB, Surface Mount
Package / Case
64-QFN
For Use With
ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Current - Transmitting
-
Current - Receiving
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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2549M–AVR–09/10
Table 12-7
shown in
MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.
PCINT0, Pin Change Interrupt source 0: The PB0 pin can serve as an external interrupt source.
Table 12-7.
Table 12-8.
DIEOE
DIEOE
Signal
DIEOV
Signal
DIEOV
PUOE
DDOE
DDOV
PUOE
DDOE
DDOV
Name
PUOV
PVOE
PVOV
Name
PUOV
PVOE
PVOV
AIO
AIO
DI
DI
Figure 12-5 on page
and
SPI SLAVE OUTPUT
OC0/OC1C ENABLE
PB7/OC0A/OC1C
SPI MSTR INPUT
Overriding Signals for Alternate Functions in PB7:PB4
Overriding Signals for Alternate Functions in PB3:PB0
PCINT3 • PCIE0
PCINT7 • PCIE0
PORTB3 • PUD
PCINT3 INPUT
PCINT7 INPUT
Table 12-8
SPE • MSTR
SPE • MSTR
SPE • MSTR
OC0/OC1C
PB3/MISO
0
1
–
0
0
0
0
1
–
relate the alternate functions of Port B to the overriding signals
76. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the
ATmega640/1280/1281/2560/2561
SPI MSTR OUTPUT
PCINT6 • PCIE0
SPI SLAVE INPUT
OC1B ENABLE
PCINT6 INPUT
PCINT2 • PCIE0
PORTB2 • PUD
PCINT2 INPUT
PB6/OC1B
SPE • MSTR
SPE • MSTR
SPE • MSTR
PB2/MOSI
OC1B
0
0
0
0
1
–
0
1
–
PCINT5 • PCIE0
OC1A ENABLE
PCINT5 INPUT
PCINT1 • PCIE0
PB5/OC1A
PORTB1 • PUD
PCINT1 INPUT
SCK OUTPUT
SPE • MSTR
SPE • MSTR
SPE • MSTR
SCK INPUT
OC1A
PB1/SCK
0
0
0
0
1
–
0
1
–
PCINT4 • PCIE0
OC2A ENABLE
PCINT4 INPUT
PCINT0 • PCIE0
PORTB0 • PUD
PCINT0 INPUT
SPE • MSTR
SPE • MSTR
PB4/OC2A
PB0/SS
OC2A
SPI SS
0
0
0
0
1
–
0
0
1
–
0
81
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