ATA8743-PXQW Atmel, ATA8743-PXQW Datasheet - Page 32

• Manufacturer Part Number: ATA8743-PXQW
• Description: MCU W/TRANSMITTER ASK/FSK 24QFN
• Manufacturer: Atmel

Specifications of ATA8743-PXQW

• Frequency: 868MHz ~ 928MHz
• Applications: Home Automation, Remote Sensing, RKE
• Modulation Or Protocol: ASK, FSK
• Data Rate - Maximum: 32 kBit/s
• Power - Output: 3.5dBm ~ 8dBm
• Current - Transmitting: 9.3mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 4kB Flash, 256B EEPROM, 256B SRAM
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
• Processor Series: ATA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 4 KB
• Data Ram Size: 256 B
• Interface Type: SPI, USI
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ATASTK512-EK1-IND
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

13.2.1
32
ATA8743
Data Memory Access Times
When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, and the 128/256/512 bytes of inter-
nal data SRAM in the ATtiny24/44/84 are all accessible through all these addressing modes.
The Register File is described in
Figure 13-2. Data Memory Map
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
page
Figure 13-3. On-chip Data SRAM Access Cycles
32.
Address
clk
Data
Data
WR
CPU
RD
(128/256/512 x 8)
64 I/O Registers
Data Memory
Internal SRAM
Compute Address
32 Registers
“General Purpose Register File” on page
T1
Memory Access Instruction
0x0DF/0x015F/0x025F
0x0000 - 0x001F
0x0020 - 0x005F
0x0060
Address valid
T2
CPU
cycles as described in
Next Instruction
T3
26.
9152B–INDCO–02/10
Figure 13-3 on