AT86RF401U-XI Atmel, AT86RF401U-XI Datasheet - Page 39

• Manufacturer Part Number: AT86RF401U-XI
• Description: IC MICRO TX RF W/AVR 20-TSSOP
• Manufacturer: Atmel

Specifications of AT86RF401U-XI

• Frequency: 264MHz ~ 456MHz
• Applications: Garage Opener, RKE, Telemetry
• Modulation Or Protocol: ASK, OOK
• Data Rate - Maximum: 10 kbps
• Power - Output: 6dBm
• Current - Transmitting: 23.2mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 2KB Flash, 128 Byte EEPROM, 128Byte SRAM
• Voltage - Supply: 2 V ~ 5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-TSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: AT86RF401U

I/O Enable Register – IO_ENAB
1424F–RKE–12/03
Initial Value
Read/Write
$30
Bit
R/W
7
–
0
When the WDE is set (“1”), the Watchdog Timer is enabled, and if the WDE is cleared
(“0”), the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE
bit is set (“1”). To disable an enabled Watchdog Timer, the following procedure must be
followed: In the same operation, write a logical “1” to WDTOE and WDE. A logical “1”
must be written to WDE even though it is set to “1” before the disable operation starts.
Within the next four clock cycles, write a logical “0” to WDE. This disables the watchdog.
• Bits[2:0]: WDP2, WDP1, WDP0, Watchdog Timer Prescaler 2, 1 and 0
The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the
Watchdog Timer is enabled. The different prescaling values and their corresponding
time-out periods are shown in Table 18.
Table 18. Watchdog Timer Prescale Select
Note:
Example:
If the crystal period is 50 ns and the system clock divider is set to 32 (Bits[7:5] in the
PWR_CTL register are set to 010) and the WDT prescaler is set to 32K, then:
Watchdog Timeout = 50 ns
• Bit[7]
Reserved.
• Bit[6]
If set to “1”, additional hysteresis is added to the battery low and brown-out logic. See
BL_CONFIG register description and Table 21 on page 43 for more details.
BOHYST
R/W
6
0
WDP2
0
0
0
0
1
1
1
1
T
wdt
=
IOE5
R/W
XTALB
5
0
WDP1
period
0
0
1
1
0
0
1
1
IOE4
R/W
4
0
32
ACS
32768 = 52 ms
div
IOE3
WDP0
R/W
3
0
0
1
0
1
0
1
0
1
WDT
div
IOE2
R/W
Number of System Clock Cycles
2,048 cycles
4,096 cycles
8,192 cycles
16,384 cycles
32,768 cycles
65,536 cycles
131,072 cycles
262,144 cycles
2
0
AT86RF401
IOE1
R/W
1
0
IOE0
R/W
0
0
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