MFRC52301HN1,151 NXP Semiconductors, MFRC52301HN1,151 Datasheet - Page 70

• Manufacturer Part Number: MFRC52301HN1,151
• Description: IC MIFARE READER 32-HVQFN
• Manufacturer: NXP Semiconductors
• Series: MIFARE®r

Specifications of MFRC52301HN1,151

• Frequency: 13.56MHz
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Operating Current: 7 mA
• Operating Voltage: 2.5 V to 3.6 V
• Product: RFID Readers
• Wireless Frequency: 13.56 MHz
• Interface Type: RS-232, I2C
• Data Rate: 100 Kbps
• Operating Temperature Range: - 25 C to +85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Rf Type: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4766; 935282956151; MFRC52301HN1

NXP Semiconductors
11. Limiting values
Table 149. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
MFRC523_34
Product data sheet
PUBLIC
Symbol
V
V
V
V
V
V
P
T
V
j
DDA
DDD
DD(PVDD)
DD(TVDD)
DD(SVDD)
I
tot
ESD
Parameter
analog supply voltage
digital supply voltage
PVDD supply voltage
TVDD supply voltage
SVDD supply voltage
input voltage
total power dissipation
junction temperature
electrostatic discharge voltage HBM; 1500 Ω, 100 pF;
10.3.1.10 SoftReset command
Remark: When the MFAuthent command is active all access to the FIFO buffer is
blocked. However, if there is access to the FIFO buffer, the ErrorReg register’s WrErr bit is
set.
This command automatically terminates when the MIFARE card is authenticated and the
Status2Reg register’s MFCrypto1On bit is set to logic 1.
This command does not terminate automatically if the card does not answer, so the timer
must be initialized to automatic mode. In this case, in addition to the IdleIRq bit, the
TimerIRq bit can be used as the termination criteria. During authentication processing, the
RxIRq bit and TxIRq bit are blocked. The Crypto1On bit is only valid after termination of
the MFAuthent command, either after processing the protocol or writing Idle to the
CommandReg register.
If an error occurs during authentication, the ErrorReg register’s ProtocolErr bit is set to
logic 1 and the Status2Reg register’s Crypto1On bit is set to logic 0.
This command performs a reset of the device. The configuration data of the internal buffer
remains unchanged. All registers are set to the reset values. This command automatically
terminates when finished.
Remark: The SerialSpeedReg register is reset and therefore the serial data rate is set to
9.6 kBd.
All information provided in this document is subject to legal disclaimers.
Conditions
all input pins except pins MFIN and
RX
pin MFIN
per package; V
mode
JESD22-A114-B
MM; 0.75 μH, 200 pF;
JESD22-A114-A
Rev. 3.5 — 24 September 2010
115235
DDD
in shortcut
Min
−0.5
−0.5
−0.5
−0.5
−0.5
V
V
-
-
-
-
SS(PVSS)
SS(PVSS)
− 0.5 V
− 0.5 V
Contactless reader IC
100
Max
+4.0
+4.0
+4.0
+4.0
+4.0
200
2000
200
MFRC523
DD(PVDD)
DD(SVDD)
© NXP B.V. 2010. All rights reserved.
+ 0.5 V
+ 0.5 V
70 of 97
Unit
V
V
V
V
V
mW
°C
V
V