MFRC52301HN1,151 NXP Semiconductors, MFRC52301HN1,151 Datasheet
MFRC52301HN1,151
Specifications of MFRC52301HN1,151
935282956151
MFRC52301HN1
Related parts for MFRC52301HN1,151
MFRC52301HN1,151 Summary of contents
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... ISO/IEC 14443-4 and/or ISO/IEC 14443 B anticollision are correctly implemented. Note that the use of this NXP Semiconductors device in accordance with ISO/IEC 14443 B may infringe on third-party patent rights the responsibility of the user to ensure that appropriate third-party patent licenses exist. ...
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... NXP Semiconductors 3. Features I Highly integrated analog circuitry to demodulate and decode responses I Buffered output drivers for connecting an antenna with the minimum number of external components I Supports ISO/IEC 14443 A/MIFARE I Supports ISO/IEC 14443 B Read/Write modes I Typical operating distance in Read/Write mode depending on the antenna size and tuning ...
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... NXP Semiconductors Table 1. Quick reference data Symbol Parameter I analog supply current DDA I PVDD supply current DD(PVDD) I TVDD supply current DD(TVDD) T ambient temperature amb [1] Supply voltages below 3 V reduce the performance in, for example, the achievable operating distance. [ and V must always be the same voltage. ...
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... NXP Semiconductors 6. Block diagram The analog interface handles the modulation and demodulation of the analog signals. The contactless UART manages the protocol requirements for the communication protocols in cooperation with the host. The FIFO buffer ensures fast and convenient data transfer to and from the host and the contactless UART and vice versa. ...
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... NXP Semiconductors SDA/NSS/RX EA I2C D1/ADR_5 SPI, UART, I FIFO CONTROL 64-BYTE FIFO BUFFER CONTROL REGISTER BANK MIFARE CLASSIC UNIT RANDOM NUMBER GENERATOR AMPLITUDE RATING REFERENCE VOLTAGE ANALOG TEST I-CHANNEL MULTIPLEXOR AMPLIFIER AND DIGITAL TO I-CHANNEL ANALOG DEMODULATOR CONVERTER VMID AUX1 AUX2 Fig 2. Detailed block diagram of the MFRC523 ...
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... NXP Semiconductors 7. Pinning information Fig 3. 7.1 Pin description Table 3. Pin description [1] Pin Symbol Type 1 I2C I 2 PVDD P 3 DVDD P 4 DVSS G 5 PVSS G 6 NRSTPD I 7 MFIN I 8 MFOUT O 9 SVDD P 10 TVSS G 11 TX1 O 12 TVDD P 13 TX2 O 14 TVSS ...
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... NXP Semiconductors Table 3. Pin description …continued [1] Pin Symbol Type 16 VMID AVSS G 19 AUX1 O 20 AUX2 O 21 OSCIN I 22 OSCOUT O 23 IRQ O 24 SDA I/O NSS I/O ADR_5 I I/O ADR_4 I/O ADR_3 I/O ADR_2 I/O ADR_1 I SCK I DTRQ I/O ADR_0 I MOSI I/O ...
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... NXP Semiconductors 8. Functional description The MFRC523 transmission module supports the Read/Write mode for ISO/IEC 14443 A/MIFARE and ISO/IEC 14443 B using various transfer speeds and modulation protocols. Fig 4. 8.1 ISO/IEC 14443 A/MIFARE functionality The physical level communication is shown in Fig 5. The physical parameters are described in Table 4 ...
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... ISO 14443 A and ISO 14443 B. Refer to the ISO 14443 reference documents Identification cards - Contactless integrated circuit cards - Proximity cards (parts 1 to 4). Remark: NXP Semiconductors does not offer a software library to enable design-in of the ISO 14443 B protocol. 8.3 Digital interfaces 8 ...
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... NXP Semiconductors Table 5. Pin 8.3.2 Serial Peripheral Interface A serial peripheral interface (SPI compatible) is supported to enable high-speed communication to the host. The interface can handle data speeds Mbit/s. When communicating with a host, the MFRC523 acts as a slave, receiving data from the external host for register settings, sending and receiving data relevant for RF interface communication ...
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... NXP Semiconductors Table 6. Line MOSI MISO [ not care. Remark: The MSB must be sent first. 8.3.2.2 SPI write data To write data to the MFRC523 using SPI requires the byte order shown in possible to write data bytes by only sending one address byte. The first send byte defines both the mode and the address byte. ...
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... NXP Semiconductors Remark: Signals DTRQ and MX can be disabled by clearing TestPinEnReg register’s RS232LineEn bit. 8.3.3.2 Selectable UART transfer speeds The internal UART interface is compatible with an RS232 serial interface. The default transfer speed is 9.6 kBd. To change the transfer speed, the host controller must write a value for the new transfer speed to the SerialSpeedReg register. Bits BR_T0[2:0] and BR_T1[4:0] defi ...
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... NXP Semiconductors transfer speed Remark: Transfer speeds above 1228.8 kBd are not supported. 8.3.3.3 UART framing Table 11. Bit Start Data Stop Remark: The LSB for data and address bytes must be sent first. No parity bit is used during transmission. Read data: To read data using the UART interface, the flow shown in used. The fi ...
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... NXP Semiconductors DTRQ (1) Reserved. Fig 9. UART read data timing diagram Write data: To write data to the MFRC523 using the UART interface, the structure shown in Table 13 The first byte sent defines both the mode and the address. Table 13. Pin RX (pin 24) TX (pin 31) ...
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ADDRESS ( DTRQ (1) Reserved. Fig 10. UART write data timing diagram Remark: The data byte can be sent directly after the address byte on pin RX. Address byte: The ...
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... An I C-bus (Inter-IC) interface is supported to enable a low-cost, low pin count serial bus interface to the host. The I NXP Semiconductors’ I interface can only act in Slave mode. Therefore the MFRC523 does not implement clock generation or access arbitration. Fig 11. I The MFRC523 can act either as a slave receiver or slave transmitter in Standard mode, Fast mode and High-speed mode ...
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... NXP Semiconductors 8.3.4.1 Data validity Data on the SDA line must be stable during the HIGH clock period. The HIGH or LOW state of the data line must only change when the clock signal on SCL is LOW. Fig 12. Bit transfer on the I 8.3.4.2 START and STOP conditions To manage the data transfer on the I are defi ...
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... NXP Semiconductors 8.3.4.4 Acknowledge An acknowledge must be sent at the end of one data byte. The acknowledge-related clock pulse is generated by the master. The transmitter of data, either master or slave, releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver pulls down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse ...
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... EA. If pin EA is set LOW, the upper 4 bits of the device bus address are reserved by NXP Semiconductors and set to 0101b for all MFRC523 devices. The remaining 3 bits (ADR_0, ADR_1, ADR_2) of the slave address can be freely configured by the customer to prevent collisions with other I If pin EA is set HIGH, ADR_0 to ADR_5 can be completely specifi ...
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... NXP Semiconductors 8.3.4.7 Register read access To read out data from a specific register address in the MFRC523, the host controller must use the following procedure: • Firstly, a write access to the specific register address must be performed as indicated in the frame that follows • ...
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... NXP Semiconductors 8.3.4.8 High-speed mode In High-speed mode (HS mode), the device can transfer information at data rates 3.4 Mbit/s, while remaining fully downward-compatible with Fast or Standard mode (F/S mode) for bidirectional communication in a mixed-speed bus system. 8.3.4.9 High-speed transfer To achieve data rates 3.4 Mbit/s the following improvements have been made to ...
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... NXP Semiconductors S SDA high SCL high Sr SDA high SCL high Master current source pull-up = Resistor pull-up 2 Fig 19. I C-bus HS mode protocol frame MFRC523_32 Product data sheet PUBLIC 8-bit master code 0000 1xxx F/S mode R/W A 7-bit SLA mode Rev. 3.2 — 12 January 2010 ...
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... NXP Semiconductors 8.3.4.11 Switching between F/S mode and HS mode After reset and initialization, the MFRC523 is in Fast mode (which is in effect F/S mode as Fast mode is downward-compatible with Standard mode). The connected MFRC523 recognizes the “S 00001XXX A” sequence and switches its internal circuitry from the Fast mode setting to the HS mode setting ...
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... NXP Semiconductors 8.4 Analog interface and contactless UART 8.4.1 General The integrated contactless UART supports the external host online with framing and error checking of the protocol requirements up to 848 kBd. An external circuit can be connected to the communication interface pins MFIN and MFOUT to modulate and demodulate the data ...
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... NXP Semiconductors Table 16. Register and bit settings controlling the signal on pin TX2 Bit Bit Bit Tx1RFEn Force Tx2CW 100ASK [ not care. The following abbreviations have been used in • RF: 13.56 MHz clock derived from 27.12 MHz quartz crystal oscillator divided by 2 • ...
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... NXP Semiconductors 8.4.3 Serial data switch Two main blocks are implemented in the MFRC523. The digital block comprises the state machines, encoder/decoder logic. The analog block comprises the modulator and antenna drivers, the receiver and amplifiers possible for the interface between these two blocks to be confi ...
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Remark: Pins MFIN and MFOUT have a dedicated supply on pin SVDD with the ground on pin PVSS. TX bit stream MILLER CODER TX serial data stream DIGITAL MODULE MFRC523 RX serial data stream 0 LOW 1 Manchester with subcarrier ...
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... NXP Semiconductors 8.4.5 CRC coprocessor The following CRC coprocessor parameters can be configured: • The CRC preset value can be either 0000h, 6363h, A671h or FFFFh depending on the ModeReg register’s CRCPreset[1:0] bits setting • The CRC polynomial for the 16-bit CRC is fixed to x • ...
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... NXP Semiconductors • FIFO buffer almost empty warning: Status1Reg register’s LoAlert bit • FIFO buffer overflow warning: ErrorReg register’s BufferOvfl bit. The BufferOvfl bit can only be cleared by setting the FIFOLevelReg register’s FlushBuffer bit. The MFRC523 can generate an interrupt signal when: • ...
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... NXP Semiconductors The ComIrqReg register’s ErrIRq bit indicates an error detected by the contactless UART during send or receive. This is indicated when any bit is set to logic 1 in register ErrorReg. Table 18. Interrupt flag TimerIRq TxIRq CRCIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq 8.7 Timer unit The MFRC523A has a timer unit which the external host can use to manage timing tasks. The timer unit can be used in one of the following timer/counter confi ...
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... NXP Semiconductors The timer can be started manually using the ControlReg register’s TStartNow bit and stopped using the ControlReg register’s TStopNow bit. The timer can also be activated automatically to meet any dedicated protocol requirements, by setting the TModeReg register’s TAuto bit to logic 1. ...
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... NXP Semiconductors 8.8 Power reduction modes 8.8.1 Hard power-down Hard power-down is enabled when pin NRSTPD is LOW. This turns off all internal current sinks including the oscillator. All digital input buffers are separated from the input pins and clamped internally (except pin NRSTPD). The output pins are frozen at either a HIGH or LOW level ...
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... NXP Semiconductors The clock applied to the MFRC523 provides a time basis for the synchronous system’s encoder and decoder. The stability of the clock frequency, therefore important factor for correct operation. To obtain optimum performance, clock jitter must be reduced as much as possible. This is best achieved using the internal oscillator buffer with the recommended circuitry ...
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... NXP Semiconductors 9. MFRC523 registers 9.1 Register bit behavior Depending on the functionality of a register, the access conditions to the register can vary. In principle, bits with same behavior are grouped in common registers. The access conditions are described in Table 19. Abbreviation Behavior R reserved RFT Table 20. ...
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... NXP Semiconductors Table 20. MFRC523 register overview Address Register name (hex) 0Dh BitFramingReg 0Eh CollReg 0Fh Reserved Page 1: Command 10h Reserved 11h ModeReg 12h TxModeReg 13h RxModeReg 14h TxControlReg 15h TxASKReg 16h TxSelReg 17h RxSelReg 18h RxThresholdReg 19h DemodReg 1Ah Reserved 1Bh ...
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... NXP Semiconductors Table 20. MFRC523 register overview Address Register name (hex) 2Eh TCounterValReg 2Fh Page 3: Test register 30h Reserved 31h TestSel1Reg 32h TestSel2Reg 33h TestPinEnReg 34h TestPinValueReg 35h TestBusReg 36h AutoTestReg 37h VersionReg 38h AnalogTestReg 39h TestDAC1Reg 3Ah TestDAC2Reg 3Bh TestADCReg 3Ch to 3Fh Reserved ...
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... NXP Semiconductors 9.2 Register descriptions 9.2.1 Page 0: Command and status 9.2.1.1 Reserved register 00h Functionality is reserved for future use. Table 21. Bit Symbol Access Table 22. Bit 9.2.1.2 CommandReg register Starts and stops command execution. Table 23. Bit Symbol: Access: Table 24. Bit Symbol reserved ...
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... NXP Semiconductors Table 26. Bit Symbol 7 IRqInv 6 TxIEn 5 RxIEn 4 IdleIEn 3 HiAlertIEn - 2 LoAlertIEn - 1 ErrIEn 0 TimerIEn 9.2.1.4 DivIEnReg register Control bits to enable and disable the passing of interrupt requests. Table 27. Bit Symbol Access Table 28. Bit Symbol 7 IRQPushPull reserved 4 MfinActIEn 3 reserved 2 CRCIEn reserved 9.2.1.5 ComIrqReg register Interrupt request bits ...
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... NXP Semiconductors Table 30. All bits in the ComIrqReg register are cleared by software. Bit Symbol 7 Set1 6 TxIRq 5 RxIRq 4 IdleIRq 3 HiAlertIRq 2 LoAlertIRq 1 1 ErrIRq 0 TimerIRq 9.2.1.6 DivIrqReg register Interrupt request bits. Table 31. Bit Symbol Access Table 32. All bits in the DivIrqReg register are cleared by software. ...
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... NXP Semiconductors 9.2.1.7 ErrorReg register Error bit register showing the error status of the last command executed. Table 33. Bit Symbol Access Table 34: Bit Symbol 7 WrErr 6 TempErr 5 reserved 4 BufferOvfl 3 CollErr 2 CRCErr 1 ParityErr 0 ProtocolErr 1 [1] Command execution clears all error bits except the TempErr bit. Cannot be set by software. ...
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... NXP Semiconductors 9.2.1.8 Status1Reg register Contains status bits of the CRC, interrupt and FIFO buffer. Table 35. Bit Symbol Access Table 36. Bit Symbol 7 reserved 6 CRCOk 5 CRCReady 1 4 IRq 3 TRunning 2 reserved 1 HiAlert 0 LoAlert MFRC523_32 Product data sheet PUBLIC Status1Reg register (address 07h); reset value: 21h bit allocation ...
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... NXP Semiconductors 9.2.1.9 Status2Reg register Contains status bits of the receiver, transmitter and data mode detector. Table 37. Bit Symbol Access Table 38. Bit MFRC523_32 Product data sheet PUBLIC Status2Reg register (address 08h); reset value: 00h bit allocation TempSensClear I CForceHS R/W R/W Status2Reg register bit descriptions ...
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... NXP Semiconductors 9.2.1.10 FIFODataReg register Input and output of 64 byte FIFO buffer. Table 39. Bit Symbol Access Table 40. Bit 9.2.1.11 FIFOLevelReg register Indicates the number of bytes stored in the FIFO. Table 41. Bit Symbol Access Table 42. Bit Symbol 7 FlushBuffer FIFOLevel [6:0] 9.2.1.12 WaterLevelReg register Defi ...
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... NXP Semiconductors Table 44. Bit 9.2.1.13 ControlReg register Miscellaneous control bits. Table 45. Bit Symbol Access Table 46. Bit reserved RxLastBits[2:0] MFRC523_32 Product data sheet PUBLIC WaterLevelReg register bit descriptions Symbol Description reserved reserved for future use WaterLevel defines a warning level to indicate a FIFO buffer overflow or underflow: [5:0] Status1Reg register’ ...
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... NXP Semiconductors 9.2.1.14 BitFramingReg register Adjustments for bit-oriented frames. Table 47. Bit Symbol Access Table 48. Bit 9.2.1.15 CollReg register Defines the first bit-collision detected on the RF interface. Table 49. Bit Symbol Access Table 50. Bit Symbol 7 ValuesAfterColl 6 reserved 5 CollPosNotValid MFRC523_32 Product data sheet PUBLIC BitFramingReg register (address 0Dh); reset value: 00h bit allocation ...
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... NXP Semiconductors Table 50. Bit Symbol CollPos[4:0] 9.2.1.16 Reserved register 0Fh Functionality is reserved for future use. Table 51. Bit Symbol Access Table 52. Bit 9.2.2 Page 1: Communication 9.2.2.1 Reserved register 10h Functionality is reserved for future use. Table 53. Bit Symbol Access Table 54. Bit MFRC523_32 Product data sheet ...
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... NXP Semiconductors 9.2.2.2 ModeReg register Defines general mode settings for transmitting and receiving. Table 55. Bit Symbol Access Table 56. Bit 9.2.2.3 TxModeReg register Defines the data rate during transmission. Table 57. Bit Symbol Access MFRC523_32 Product data sheet PUBLIC ModeReg register (address 11h); reset value: 3Fh bit allocation ...
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... NXP Semiconductors Table 58. Bit 9.2.2.4 RxModeReg register Defines the data rate during reception. Table 59. Bit Symbol Access Table 60. Bit MFRC523_32 Product data sheet PUBLIC TxModeReg register bit descriptions Symbol Value TxCRCEn 1 TxSpeed[2:0] 000 001 010 011 100 101 110 111 InvMod ...
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... NXP Semiconductors Table 60. Bit 9.2.2.5 TxControlReg register Controls the logical behavior of the antenna driver pins TX1 and TX2. Table 61. Bit Symbol InvTx2RF Access Table 62. Bit Symbol 7 InvTx2RFOn 1 6 InvTx1RFOn 1 5 InvTx2RFOff 1 4 InvTx1RFOff 1 3 Tx2CW 2 reserved 1 Tx2RFEn 0 Tx1RFEn MFRC523_32 Product data sheet ...
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... NXP Semiconductors 9.2.2.6 TxASKReg register Controls transmit modulation settings. Table 63. Bit Symbol Access Table 64. Bit Symbol 7 reserved 6 Force100ASK reserved 9.2.2.7 TxSelReg register Selects the internal sources for the analog module. Table 65. Bit Symbol: Access: Table 66. Bit MFRC523_32 Product data sheet PUBLIC TxASKReg register (address 15h) ...
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... NXP Semiconductors Table 66. Bit 9.2.2.8 RxSelReg register Selects internal receiver settings. Table 67. Bit Symbol Access Table 68. Bit MFRC523_32 Product data sheet PUBLIC TxSelReg register bit descriptions Symbol Value Description MFOutSel selects the input for pin MFOUT [3:0] 0000 3-state 0001 LOW ...
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... NXP Semiconductors 9.2.2.9 RxThresholdReg register Selects thresholds for the bit decoder. Table 69. Bit Symbol Access Table 70. Bit 9.2.2.10 DemodReg register Defines demodulator settings. Table 71. Bit Symbol Access Table 72. Bit 9.2.2.11 Reserved register 1Ah Functionality is reserved for future use. MFRC523_32 Product data sheet PUBLIC RxThresholdReg register (address 18h) ...
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... NXP Semiconductors Table 73. Bit Symbol Access Table 74. Bit 9.2.2.12 Reserved register 1Bh Functionality is reserved for future use. Table 75. Bit Symbol Access Table 76. Bit 9.2.2.13 MfTxReg register Controls some MIFARE communication transmit parameters. Table 77. Bit Symbol Access Table 78. Bit MFRC523_32 Product data sheet PUBLIC Reserved register (address 1Ah) ...
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... NXP Semiconductors 9.2.2.14 MfRxReg register Table 79. Bit Symbol Access Table 80. Bit Symbol reserved 4 ParityDisable reserved 9.2.2.15 TypeBReg register Configures the ISO/IEC 14443 B functionality. Table 81. Bit Symbol Access Table 82. Bit MFRC523_32 Product data sheet PUBLIC MfRxReg register (address 1Dh); reset value: 00h bit allocation ...
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... NXP Semiconductors 9.2.2.16 SerialSpeedReg register Selects the speed of the serial UART interface. Table 83. Bit Symbol Access Table 84. Bit MFRC523_32 Product data sheet PUBLIC SerialSpeedReg register (address 1Fh); reset value: EBh bit allocation BR_T0[2:0] R/W SerialSpeedReg register bit descriptions Symbol Description BR_T0[2:0] factor BR_T0 adjusts the transfer speed: for description, see Section 8 ...
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... NXP Semiconductors 9.2.3 Page 2: Configuration 9.2.3.1 Reserved register 20h Functionality is reserved for future use. Table 85. Bit Symbol Access Table 86. Bit 9.2.3.2 CRCResultReg registers Shows the MSB and LSB values of the CRC calculation. Remark: The CRC is split into two 8-bit registers. ...
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... NXP Semiconductors 9.2.3.3 Reserved register 23h Functionality is reserved for future use. Table 91. Bit Symbol Access Table 92. Bit 9.2.3.4 ModWidthReg register Sets the modulation width. Table 93. Bit Symbol Access Table 94. Bit 9.2.3.5 Reserved register 25h Functionality is reserved for future use. Table 95. ...
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... NXP Semiconductors 9.2.3.6 RFCfgReg register Configures the receiver gain. Table 97. Bit Symbol Access Table 98. Bit 9.2.3.7 GsNReg register Defines the conductance of the antenna driver pins TX1 and TX2 for the n-driver when the driver is switched on. Table 99. Bit Symbol Access Table 100. GsNReg register bit descriptions ...
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... NXP Semiconductors 9.2.3.8 CWGsPReg register Defines the conductance of the p-driver output during periods of no modulation. Table 101. CWGsPReg register (address 28h); reset value: 20h bit allocation Bit Symbol Access Table 102. CWGsPReg register bit descriptions Bit 9.2.3.9 ModGsPReg register Defines the conductance of the p-driver output during modulation. ...
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... NXP Semiconductors Table 106. TModeReg register bit descriptions Bit Table 107. TPrescalerReg register (address 2Bh); reset value: 00h bit allocation Bit Symbol Access Table 108. TPrescalerReg register bit descriptions Bit 9.2.3.11 TReloadReg register Defines the 16-bit timer reload value. MFRC523_32 Product data sheet ...
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... NXP Semiconductors Remark: The reload value bits are contained in two 8-bit registers. Table 109. TReloadReg (higher bits) register (address 2Ch); reset value: 00h bit allocation Bit Symbol Access Table 110. TReloadReg register higher bit descriptions Bit Table 111. TReloadReg (lower bits) register (address 2Dh); reset value: 00h bit allocation ...
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... NXP Semiconductors Table 116. TCounterValReg register lower bit descriptions Bit 9.2.4 Page 3: Test 9.2.4.1 Reserved register 30h Functionality is reserved for future use. Table 117. Reserved register (address 30h); reset value: 00h bit allocation Bit Symbol Access Table 118. Reserved register bit descriptions ...
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... NXP Semiconductors Table 122. TestSel2Reg register bit descriptions Bit Symbol 7 TstBusFlip 1 6 PRBS9 5 PRBS15 TestBusSel [4:0] 9.2.4.4 TestPinEnReg register Enables the test bus pin output driver. Table 123. TestPinEnReg register (address 33h); reset value: 80h bit allocation Bit Symbol Access Table 124. TestPinEnReg register bit descriptions ...
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... NXP Semiconductors Table 126. TestPinValueReg register bit descriptions Bit TestPinValue 0 9.2.4.6 TestBusReg register Shows the status of the internal test bus. Table 127. TestBusReg register (address 35h); reset value: xxh bit allocation Bit Symbol Access Table 128. TestBusReg register bit descriptions Bit ...
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... NXP Semiconductors Table 130. AutoTestReg register bit descriptions Bit 9.2.4.8 VersionReg register Shows the MFRC523 software version. Table 131. VersionReg register (address 37h); reset value: xxh bit allocation Bit Symbol Access Table 132. VersionReg register bit descriptions Bit 9.2.4.9 AnalogTestReg register Determines the analog output test signal at, and status of, pins AUX1 and AUX2. Table 133. AnalogTestReg register (address 38h) ...
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... NXP Semiconductors Table 134. AnalogTestReg register bit descriptions Bit AnalogSelAux1 AnalogSelAux2 [1] Remark: Current source output; the use pull-down resistor on AUXn is recommended. MFRC523_32 Product data sheet PUBLIC Symbol Value Description controls pin AUX1 [3:0] 0000 3-state 0001 output of TestDAC1 (AUX1), output of TestDAC2 (AUX2) ...
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... NXP Semiconductors 9.2.4.10 TestDAC1Reg register Defines the test value for TestDAC1. Table 135. TestDAC1Reg register (address 39h); reset value: xxh bit allocation Bit Symbol Access Table 136. TestDAC1Reg register bit descriptions Bit 9.2.4.11 TestDAC2Reg register Defines the test value for TestDAC2. ...
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... NXP Semiconductors Table 141. Reserved register (address 3Ch); reset value: FFh bit allocation Bit Symbol Access Table 142. Reserved register bit descriptions Bit Table 143. Reserved register (address 3Dh); reset value: 00h bit allocation Bit Symbol Access Table 144. Reserved register bit descriptions ...
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... NXP Semiconductors 10.1 General description The MFRC523 operation is determined by a state machine capable of performing a set of commands. A command is executed by writing a command code (see CommandReg register. Arguments and/or data necessary to process a command are exchanged via the FIFO buffer. 10.2 General behavior • Each command that needs a data bit stream (or data byte stream input immediately processes any data in the FIFO buffer ...
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... NXP Semiconductors 10.3.1.2 Mem Transfers 25 bytes from the FIFO buffer to the internal buffer. To read out the 25 bytes from the internal buffer the Mem command must be started with an empty FIFO buffer. In this case, the 25 bytes are transferred from the internal buffer to the FIFO. ...
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... NXP Semiconductors This command automatically terminates when the data stream ends. This is indicated either by the end of frame pattern or by the length byte depending on the selected frame type and speed. Remark: If the RxModeReg register’s RxMultiple bit is set to logic 1, the Receive command will not automatically terminate. It must be terminated by starting another command in the CommandReg register ...
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... NXP Semiconductors RxIRq bit and TxIRq bit are blocked. The Crypto1On bit is only valid after termination of the MFAuthent command, either after processing the protocol or writing Idle to the CommandReg register error occurs during authentication, the ErrorReg register’s ProtocolErr bit is set to logic 1 and the Status2Reg register’s Crypto1On bit is set to logic 0. ...
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... NXP Semiconductors Table 151. Operating conditions Symbol Parameter V PVDD supply voltage DD(PVDD) V SVDD supply voltage DD(SVDD) T ambient temperature amb [1] Supply voltages below 3 V reduce the performance (the achievable operating distance). [ and V must always be the same voltage. DDA DDD DD(TVDD) [3] V must always be the same or lower voltage than V DD(PVDD) 13 ...
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... NXP Semiconductors Table 153. Characteristics …continued Symbol Parameter V maximum peak-to-peak input i(p-p)(max) voltage Input sensitivity; see Figure 24 V modulation voltage mod Pin OSCIN I input leakage current LI V HIGH-level input voltage IH V LOW-level input voltage IL C input capacitance i Input/output characteristics pins D1, D2, D3, D4, D5, D6 and D7 ...
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... NXP Semiconductors Table 153. Characteristics …continued Symbol Parameter Pins TX1 and TX2 V HIGH-level output voltage OH V LOW-level output voltage OL Current consumption I power-down current pd I digital supply current DDD I analog supply current DDA I PVDD supply current DD(PVDD) I TVDD supply current DD(TVDD) I SVDD supply current ...
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... NXP Semiconductors Table 153. Characteristics …continued Symbol Parameter V LOW-level output voltage OL C input capacitance i Typical input requirements f crystal frequency xtal ESR equivalent series resistance C load capacitance L P crystal power dissipation xtal [1] The voltage on pin RX is clamped by internal diodes to pins AVSS and AVDD. ...
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... NXP Semiconductors Table 154. SPI timing characteristics Symbol t su(D-SCKH) t h(SCKL-Q) t (SCKL-NSSH) Table 155. I Symbol Parameter f SCL t HD;STA t SU;STA t SU;STO t LOW t HIGH t HD;DAT t SU;DAT BUF MFRC523_32 Product data sheet PUBLIC …continued Parameter Conditions data input to SCK HIGH changing MOSI to set-up time SCK ...
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... NXP Semiconductors SCK MOSI MISO NSS Fig 25. Timing diagram for SPI SDA SCL Fig 26. Timing for Fast and Standard mode devices on the I MFRC523_32 Product data sheet PUBLIC t t SCKL SCKH t t DXSH SHDX MSB MSB Remark: The signal NSS must be LOW to be able to send several bytes in one data stream. ...
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... NXP Semiconductors 15. Application information A typical application diagram using a complementary antenna connection to the MFRC523 is shown in The antenna tuning and RF part matching is described in the application note Ref. 2. NRSTPD interface MICRO- PROCESSOR Fig 27. Typical application diagram MFRC523_32 Product data sheet PUBLIC Figure 27. supply DVDD ...
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... NXP Semiconductors 16. Test information 16.1 Test signals 16.1.1 Self test The MFRC523 has the capability to perform a digital self test. The self test is started by using the following procedure: 1. Perform a soft reset. 2. Clear the internal buffer by writing 25 bytes of 00h and implement the Config command ...
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... NXP Semiconductors Table 157. Test bus signals: TestBusSel[4:0] = 0Dh Pins 16.1.3 Test signals on pins AUX1 or AUX2 The MFRC523 allows the user to select internal signals for measurement on pins AUX1 or AUX2. These measurements can be helpful during the design-in phase to optimize the design or used for test purposes. ...
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... NXP Semiconductors Figure 28 TestDAC1Reg register is programmed with a slope defined by values 00h to 3Fh and the TestDAC2Reg register is programmed with a rectangular signal defined by values 00h and 3Fh. (1) TestDAC1 (500 mV/div) on pin AUX1. (2) TestDAC2 (500 mV/div) on pin AUX2. Fig 28. Output test signals TestDAC1 on pin AUX1 and TestDAC2 on pin AUX2 16 ...
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... NXP Semiconductors 16.1.3.3 Example: Output test signals ADC channel I and ADC channel Q Figure 30 AUX2, respectively. The AnalogTestReg register is set to 56h. (1) ADC_I (1 V/div) on pin AUX1. (2) ADC_Q (500 mV/div) on pin AUX2. (3) RF field. Fig 30. Output ADC channel I on pin AUX1 and ADC channel Q on pin AUX2 16 ...
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... NXP Semiconductors (1) RxActive (2 V/div) on pin AUX1. (2) TxActive (2 V/div) on pin AUX2. (3) RF field. Fig 31. Output RxActive on pin AUX1 and TxActive on pin AUX2 MFRC523_32 Product data sheet PUBLIC Rev. 3.2 — 12 January 2010 115232 MFRC523 Contactless reader IC 001aak600 (1) (2) (3) 10 s/div © NXP B.V. 2010. All rights reserved. ...
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... NXP Semiconductors 16.1.3.5 Example: Output test signal RX data stream Figure 32 register’s TestBusSel[4:0] bits are set to 07h to enable test bus signals on pins D1 to D6; see Section 16.1.2 on page 06h (pin D6 = s_data) and AnalogTestReg register is set to FFh (TstBusBit) which outputs the received data stream on pins AUX1 and AUX2. ...
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... NXP Semiconductors 17. Package outline HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 0.85 mm terminal 1 index area terminal 1 index area 32 DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors Detailed package information can be found at: http://www.nxp.com/package/SOT617-1.html. 18. Handling information Moisture Sensitivity Level (MSL) evaluation has been performed according to SNW-FQ-225B rev.04/07/07 (JEDEC J-STD-020C) . MSL for this package is level 1 which means 260 C convection reflow temperature. Dry pack is not required. Unlimited out-of-pack floor life at maximum ambient 30 C/85 % RH. ...
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... NXP Semiconductors The straps around the package of stacked trays inside the piano-box have sufficient pre-tension to avoid loosening of the trays. chamfer PIN 1 chamfer PIN 1 printed piano box Fig 35. Packing information 5 trays MFRC523_32 Product data sheet PUBLIC strap 46 mm from corner tray In the traystack (2 trays) only ONE tray type* allowed *one supplier and one revision number ...
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... NXP Semiconductors 20. Abbreviations Table 159. Abbreviations Acronym ADC ASK BPSK CRC CW DAC HBM LSB MISO MM MOSI MSB NRZ NSS PCB PLL PRBS RX SOF SPI TX UART 21. Glossary Modulation index — Defined as the voltage ratio (V Load modulation index — Defined as the voltage ratio for the card ...
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... NXP Semiconductors 23. Revision history Table 160. Revision history Document ID Release date MFRC523_32 20100112 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 25. Contact information For more information, please visit: For sales office addresses, please send an email to: MFRC523_32 Product data sheet PUBLIC http://www.nxp.com salesaddresses@nxp.com Rev. 3.2 — 12 January 2010 115232 MFRC523 Contactless reader IC © NXP B.V. 2010. All rights reserved ...
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... NXP Semiconductors 26. Tables Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .2 Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .6 Table 4. Communication overview for ISO/IEC 14443 A/MIFARE reader/writer . . . . . .8 Table 5. Connection protocol for detecting different interface types . . . . . . . . . . . . . . . . . . . . . . . . . .9 Table 6. MOSI and MISO byte order . . . . . . . . . . . . . . .11 Table 7. MOSI and MISO byte order . . . . . . . . . . . . . . .11 Table 8. Address byte 0 register ...
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... NXP Semiconductors Table 68. RxSelReg register bit descriptions . . . . . . . . . .51 Table 69. RxThresholdReg register (address 18h); reset value: 84h bit allocation . . . . . . . . . . . . .52 Table 70. RxThresholdReg register bit descriptions . . . .52 Table 71. DemodReg register (address 19h); reset value: 4Dh bit allocation . . . . . . . . . . . . .52 Table 72. DemodReg register bit descriptions . . . . . . . . .52 Table 73. Reserved register (address 1Ah); ...
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... NXP Semiconductors Table 128.TestBusReg register bit descriptions . . . . . . . .64 Table 129.AutoTestReg register (address 36h); reset value: 40h bit allocation . . . . . . . . . . . . .64 Table 130.AutoTestReg register bit descriptions . . . . . . .65 Table 131.VersionReg register (address 37h); reset value: xxh bit allocation . . . . . . . . . . . . . .65 Table 132.VersionReg register bit descriptions . . . . . . . .65 Table 133.AnalogTestReg register (address 38h); ...
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... NXP Semiconductors 27. Figures Fig 1. Simplified block diagram of the MFRC523 Fig 2. Detailed block diagram of the MFRC523 . . . . . . . .5 Fig 3. Pinning configuration HVQFN32 (SOT617- Fig 4. MFRC523 Read/Write mode . . . . . . . . . . . . . . . . .8 Fig 5. ISO/IEC 14443 A/MIFARE Read/Write mode communication diagram Fig 6. Data coding and framing according to ISO/IEC 14443 Fig 7 ...
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... NXP Semiconductors 28. Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 General description . . . . . . . . . . . . . . . . . . . . . . 1 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 7.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 Functional description . . . . . . . . . . . . . . . . . . . 8 8.1 ISO/IEC 14443 A/MIFARE functionality . . . . . . 8 8.2 ISO/IEC 14443 B functionality . . . . . . . . . . . . . 9 8.3 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . 9 8.3.1 Automatic microcontroller interface detection ...
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... NXP Semiconductors 9.2.3.3 Reserved register 23h . . . . . . . . . . . . . . . . . . 57 9.2.3.4 ModWidthReg register . . . . . . . . . . . . . . . . . . 57 9.2.3.5 Reserved register 25h . . . . . . . . . . . . . . . . . . 57 9.2.3.6 RFCfgReg register . . . . . . . . . . . . . . . . . . . . . 58 9.2.3.7 GsNReg register . . . . . . . . . . . . . . . . . . . . . . . 58 9.2.3.8 CWGsPReg register . . . . . . . . . . . . . . . . . . . . 59 9.2.3.9 ModGsPReg register . . . . . . . . . . . . . . . . . . . 59 9.2.3.10 TModeReg and TPrescalerReg registers . . . . 59 9.2.3.11 TReloadReg register 9.2.3.12 TCounterValReg register . . . . . . . . . . . . . . . . 61 9.2.4 Page 3: Test . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.2.4.1 Reserved register 30h . . . . . . . . . . . . . . . . . . 62 9 ...