CLRC63201T/0FE,112 NXP Semiconductors, CLRC63201T/0FE,112 Datasheet - Page 121

• Manufacturer Part Number: CLRC63201T/0FE,112
• Description: IC I.CODE HS READER 32-SOIC
• Manufacturer: NXP Semiconductors
• Series: I-Coder

Specifications of CLRC63201T/0FE,112

• Rf Type: Read Only
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B, ISO15693, ISO18000-3
• Package / Case: 32-SOIC (0.300", 7.50mm Width)
• Product: RFID Readers
• Operating Temperature Range: - 25 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2199-5; 935269690112; CLRC632; CLRC63201TD

NXP Semiconductors
22. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. SPI write address . . . . . . . . . . . . . . . . . . . . . .11
Table 11. EEPROM memory organization diagram . . . . .12
Table 12. Product information field . . . . . . . . . . . . . . . . .13
Table 13. Product type identification definition . . . . . . . .13
Table 14. Byte assignment for register initialization at
Table 15. Shipment content of StartUp configuration file 15
Table 16. Byte assignment for register initialization at
Table 17. Content of I-CODE1 startup configuration . . . .17
Table 18. FIFO buffer access . . . . . . . . . . . . . . . . . . . . .19
Table 19. Associated FIFO buffer registers and flags . . .20
Table 20. Interrupt sources . . . . . . . . . . . . . . . . . . . . . . .21
Table 21. Interrupt control registers . . . . . . . . . . . . . . . .21
Table 22. Associated Interrupt request system registers
Table 23. TimeSlotPeriod . . . . . . . . . . . . . . . . . . . . . . . .26
Table 24. Associated timer unit registers and flags . . . . .27
Table 25. Signal on pins during Hard power-down . . . . .28
Table 26. Pin TX1 configurations . . . . . . . . . . . . . . . . . . .31
Table 27. Pin TX2 configurations . . . . . . . . . . . . . . . . . . .32
Table 28. TX1 and TX2 source resistance of
Table 29. Gain factors for the internal amplifier . . . . . . . .36
Table 30. DecoderSource[1:0] values . . . . . . . . . . . . . . .39
Table 31. ModulatorSource[1:0] values . . . . . . . . . . . . . .39
Table 32. MFOUTSelect[2:0] values . . . . . . . . . . . . . . . .39
Table 33. Register settings to enable use of the analog
Table 34. MIFARE higher baud rates . . . . . . . . . . . . . . .40
Table 35. ISO/IEC 14443 B registers and flags . . . . . . . .41
Table 36. Dedicated address bus: assembling the
Table 37. Multiplexed address bus: assembling the
Table 38. Behavior and designation of register bits . . . . .44
CLRC632_35
Product data sheet
PUBLIC
Quick reference data . . . . . . . . . . . . . . . . . . . . .3
Ordering information . . . . . . . . . . . . . . . . . . . . .3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
Supported microprocessor and EPP
interface signals . . . . . . . . . . . . . . . . . . . . . . . . .7
Connection scheme for detecting the
parallel interface type . . . . . . . . . . . . . . . . . . . . .8
SPI compatibility . . . . . . . . . . . . . . . . . . . . . . .10
SPI read data . . . . . . . . . . . . . . . . . . . . . . . . . .10
SPI read address . . . . . . . . . . . . . . . . . . . . . . .11
SPI write data . . . . . . . . . . . . . . . . . . . . . . . . .11
start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
startup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
and flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
n-channel driver transistor against
GsCfgCW or GsCfgMod . . . . . . . . . . . . . . . . .33
circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
register address . . . . . . . . . . . . . . . . . . . . . . . .43
register address . . . . . . . . . . . . . . . . . . . . . . . .44
Rev. 3.5 — 10 November 2009
Multiple protocol contactless reader IC (MIFARE/I-CODE1)
073935
Table 39. CLRC632 register overview . . . . . . . . . . . . . . 45
Table 40. CLRC632 register flags overview . . . . . . . . . . 47
Table 41. Page register (address: 00h, 08h, 10h,
Table 42. Page register bit descriptions . . . . . . . . . . . . . 50
Table 43. Command register (address: 01h)
Table 44. Command register bit descriptions . . . . . . . . . 50
Table 45. FIFOData register (address: 02h)
Table 46. FIFOData register bit descriptions . . . . . . . . . 51
Table 47. PrimaryStatus register (address: 03h)
Table 48. PrimaryStatus register bit descriptions . . . . . . 51
Table 49. FIFOLength register (address: 04h)
Table 50. FIFOLength bit descriptions . . . . . . . . . . . . . . 52
Table 51. SecondaryStatus register (address: 05h)
Table 52. SecondaryStatus register bit descriptions . . . . 53
Table 53. InterruptEn register (address: 06h)
Table 54. InterruptEn register bit descriptions . . . . . . . . 53
Table 55. InterruptRq register (address: 07h)
Table 56. InterruptRq register bit descriptions . . . . . . . . 54
Table 57. Control register (address: 09h)
Table 58. Control register bit descriptions . . . . . . . . . . . . 55
Table 59. ErrorFlag register (address: 0Ah)
Table 60. ErrorFlag register bit descriptions . . . . . . . . . . 55
Table 61. CollPos register (address: 0Bh)
Table 62. CollPos register bit descriptions . . . . . . . . . . . 56
Table 63. TimerValue register (address: 0Ch)
Table 64. TimerValue register bit descriptions . . . . . . . . 57
Table 65. CRCResultLSB register (address: 0Dh)
Table 66. CRCResultLSB register bit descriptions . . . . . 57
Table 67. CRCResultMSB register (address: 0Eh)
Table 68. CRCResultMSB register bit descriptions . . . . 57
Table 69. BitFraming register (address: 0Fh)
Table 70. BitFraming register bit descriptions . . . . . . . . . 58
18h, 20h, 28h, 30h, 38h) reset value:
1000 0000b, 80h bit allocation . . . . . . . . . . . . 50
reset value: x000 0000b, x0h bit allocation . . . 50
reset value: xxxx xxxxb, 05h bit allocation . . . 51
reset value: 0000 0101b, 05h bit allocation . . . 51
reset value: 0000 0000b, 00h bit allocation . . . 52
reset value: 01100 000b, 60h bit allocation . . . 53
reset value: 0000 0000b, 00h bit allocation . . . 53
reset value: 0000 0000b, 00h bit allocation . . . 54
reset value: 0000 0000b, 00h bit allocation . . . 55
reset value: 0100 0000b, 40h bit allocation . . . 55
reset value: 0000 0000b, 00h bit allocation . . . 56
reset value: xxxx xxxxb, xxh bit allocation . . . . 57
reset value: xxxx xxxxb, xxh bit allocation . . . . 57
reset value: xxxx xxxxb, xxh bit allocation . . . . 57
reset value: 0000 0000b, 00h bit allocation . . . 58
CLRC632
© NXP B.V. 2009. All rights reserved.
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