PIC18F24K22-I/SO Microchip Technology, PIC18F24K22-I/SO Datasheet - Page 107

• Manufacturer Part Number: PIC18F24K22-I/SO
• Description: IC PIC MCU 16KB FLASH 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F24K22-I/SO

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 19x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 64MHz
• No. Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.3
To read a data memory location, the user must write
the address to the EEADR register, clear the EEPGD
control bit of the EECON1 register and then set control
bit, RD. The data is available on the very next instruc-
tion cycle; therefore, the EEDATA register can be read
by the next instruction. EEDATA will hold this value until
another read operation, or until it is written to by the
user (during a write operation).
The basic process is shown in
7.4
To write an EEPROM data location, the address must
first be written to the EEADR register and the data writ-
ten to the EEDATA register. The sequence in
Example 7-2
The write will not begin if this sequence is not exactly
followed (write 55h to EECON2, write 0AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.
EXAMPLE 7-1:
EXAMPLE 7-2:
 2010 Microchip Technology Inc.
Required
Sequence
Reading the Data EEPROM
Memory
Writing to the Data EEPROM
Memory
MOVLW
MOVWF
BCF
BCF
BSF
MOVF
must be followed to initiate the write cycle.
DATA_EE_ADDR
EEADR
EECON1, EEPGD
EECON1, CFGS
EECON1, RD
EEDATA, W
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
DATA EEPROM READ
DATA EEPROM WRITE
DATA_EE_ADDR_LOW
EEADR
DATA_EE_ADDR_HI
EEADRH
DATA_EE_DATA
EEDATA
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
EECON1, WREN
Example
;
; Data Memory Address to read
; Point to DATA memory
; Access EEPROM
; EEPROM Read
; W = EEDATA
7-1.
;
; Data Memory Address to write
;
;
;
; Data Memory Value to write
; Point to DATA memory
; Access EEPROM
; Enable writes
; Disable Interrupts
;
; Write 55h
;
; Write 0AAh
; Set WR bit to begin write
; Enable Interrupts
; User code execution
; Disable writes on write complete (EEIF set)
Preliminary
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code
execution (i.e., runaway programs). The WREN bit
should be kept clear at all times, except when updating
the EEPROM. The WREN bit is not cleared by
hardware.
After a write sequence has been initiated, EECON1,
EEADR and EEDATA cannot be modified. The WR bit
will be inhibited from being set unless the WREN bit is
set. Both WR and WREN cannot be set with the same
instruction.
At the completion of the write cycle, the WR bit is
cleared by hardware and the EEPROM Interrupt Flag
bit, EEIF, is set. The user may either enable this
interrupt or poll this bit. EEIF must be cleared by
software.
7.5
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
PIC18(L)F2X/4XK22
Write Verify
DS41412D-page 107