PIC18LF26K22-I/ML Microchip Technology, PIC18LF26K22-I/ML Datasheet - Page 248
![IC PIC MCU 64KB FLASH 28QFN](/photos/19/6/190629/4733462_sml.jpg)
PIC18LF26K22-I/ML
Manufacturer Part Number
PIC18LF26K22-I/ML
Description
IC PIC MCU 64KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18LF26K22-I/ML
Core Size
8-Bit
Program Memory Size
64KB (32K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 19x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
1KB
Ram Memory Size
3896Byte
Cpu Speed
64MHz
No. Of Timers
7
Processor Series
PIC18LF
Core
PIC
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC18(L)F2X/4XK22
15.6.13
Multi-Master mode support is achieved by bus
arbitration. When the master outputs address/data bits
onto the SDAx pin, arbitration takes place when the
master outputs a ‘1’ on SDAx, by letting SDAx float high
and another master asserts a ‘0’. When the SCLx pin
floats high, data should be stable. If the expected data
on SDAx is a ‘1’ and the data sampled on the SDAx pin
is ‘0’, then a bus collision has taken place. The master
will set the Bus Collision Interrupt Flag, BCLxIF, and
reset the I
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDAx and SCLx lines are deasserted and
the SSPxBUF can be written to. When the user
services the bus collision Interrupt Service Routine and
if the I
communication by asserting a Start condition.
FIGURE 15-32:
DS41412D-page 248
SDAx
SCLx
BCLxIF
2
C bus is free, the user can resume
2
C port to its Idle state
MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATION
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Data changes
while SCLx = 0
(Figure
15-31).
Preliminary
SDAx released
by master
SDAx line pulled low
by another source
If a Start, Repeated Start, Stop or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDAx and SCLx
lines are deasserted and the respective control bits in
the SSPxCON2 register are cleared. When the user
services the bus collision Interrupt Service Routine and
if the I
communication by asserting a Start condition.
The master will continue to monitor the SDAx and SCLx
pins. If a Stop condition occurs, the SSPxIF bit will be set.
A write to the SSPxBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the
determination of when the bus is free. Control of the I
bus can be taken when the P bit is set in the SSPxSTAT
register, or the bus is Idle and the S and P bits are
cleared.
2
C bus is free, the user can resume
Sample SDAx. While SCLx is high,
data does not match what is driven
by the master.
Bus collision has occurred.
Set bus collision
interrupt (BCLxIF)
2010 Microchip Technology Inc.
2
C
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