PIC18LF26K22-I/ML Microchip Technology, PIC18LF26K22-I/ML Datasheet - Page 272
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PIC18LF26K22-I/ML
Manufacturer Part Number
PIC18LF26K22-I/ML
Description
IC PIC MCU 64KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18LF26K22-I/ML
Core Size
8-Bit
Program Memory Size
64KB (32K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 19x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
1KB
Ram Memory Size
3896Byte
Cpu Speed
64MHz
No. Of Timers
7
Processor Series
PIC18LF
Core
PIC
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC18(L)F2X/4XK22
16.2
The factory calibrates the internal oscillator block
output
frequency may drift as V
and this directly affects the asynchronous baud rate.
Two methods may be used to adjust the baud rate
clock, but both require a reference clock source of
some kind.
REGISTER 16-1:
DS41412D-page 272
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
R/W-0
CSRC
(HFINTOSC).
Clock Accuracy with
Asynchronous Operation
SREN/CREN overrides TXEN in Sync mode.
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care
Synchronous mode:
1 =
0 =
TX9: 9-bit Transmit Enable bit
1 =
0 =
TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
SYNC: EUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
SENDB: Send Break Character bit
Asynchronous mode:
1 = Send Sync Break on next transmission (cleared by hardware upon completion)
0 = Sync Break transmission completed
Synchronous mode:
Don’t care
BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode
TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
TX9D: Ninth bit of Transmit Data
Can be address/data bit or a parity bit.
R/W-0
TX9
Master mode (clock generated internally from BRG)
Slave mode (clock from external source)
Selects 9-bit transmission
Selects 8-bit transmission
TXSTAX: TRANSMIT STATUS AND CONTROL REGISTER
However,
DD
or temperature changes,
W = Writable bit
‘1’ = Bit is set
TXEN
R/W-0
the
(1)
(1)
HFINTOSC
R/W-0
SYNC
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SENDB
R/W-0
The first (preferred) method uses the OSCTUNE
register to adjust the HFINTOSC output. Adjusting the
value in the OSCTUNE register allows for fine resolution
changes to the system clock source. See
“Internal Clock Modes”
The other method adjusts the value in the Baud Rate
Generator. This can be done automatically with the
Auto-Baud Detect feature (see
Baud
resolution when adjusting the Baud Rate Generator to
compensate for a gradual change in the peripheral
clock frequency.
Detect”). There may not be fine enough
BRGH
R/W-0
2010 Microchip Technology Inc.
for more information.
x = Bit is unknown
TRMT
R-1
Section 16.3.1 “Auto-
Section 2.5
R/W-0
TX9D
bit 0
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