ST16C450CQ48-F Exar Corporation, ST16C450CQ48-F Datasheet - Page 14

• Manufacturer Part Number: ST16C450CQ48-F
• Description: IC UART SINGLE 48TQFP
• Manufacturer: Exar Corporation
• Type: UARTsr

Specifications of ST16C450CQ48-F

• Package / Case: 48-TQFP
• Features: *
• Number Of Channels: 1, UART
• Fifo's: 1 Byte
• Voltage - Supply: 2.97 V ~ 5.5 V
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 1.5 Mbps
• Supply Current: 3 mA
• Maximum Operating Temperature: 0 C
• Minimum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 7 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ST16C450
ISR BIT-0:
Logic 0 = An interrupt is pending and the ISR contents
may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending. (normal default condi-
tion)
ISR BIT 1-3: (logic 0 or cleared is the default condition)
These bits indicate the source for a pending interrupt
at interrupt priority levels 1, 2, and 3 (See Interrupt
Source Table).
ISR BIT 4-7 : Not used and set to “0”.
Line Control Register (LCR)
The Line Control Register is used to specify the
asynchronous data communication format. The word
length, the number of stop bits, and the parity are
selected by writing the appropriate bits in this register.
LCR BIT 0-1: (logic 0 or cleared is the default condi-
tion)
These two bits specify the word length to be transmit-
ted or received.
BIT-1
Priority
Rev. 4.20
Level
0
0
1
1
1
2
3
4
Table 5, INTERRUPT SOURCE TABLE
BIT-0
Bit-3 Bit-2Bit-1
0
0
1
0
1
0
0
0
1
1
0
0
[ISR]
Word length
1
0
1
0
5
6
7
8
Bit-0
0
0
0
0
Source of the interrupt
LSR (Receiver Line Status Register)
RXRDY (Received Data Ready)
TXRDY ( Transmitter Holding Register Empty)
MSR (Modem Status Register)
14
LCR BIT-2: (logic 0 or cleared is the default condition)
The length of stop bit is specified by this bit in conjunc-
tion with the programmed word length.
LCR BIT-3:
Parity or no parity can be selected via this bit.
Logic 0 = No parity (normal default condition)
Logic 1 = A parity bit is generated during the transmis-
sion, receiver checks the data and parity for transmis-
sion errors.
LCR BIT-4:
If the parity bit is enabled with LCR bit-3 set to a logic
1, LCR BIT-4 selects the even or odd parity format.
Logic 0 = ODD Parity is generated by forcing an odd
number of logic 1’s in the transmitted data. The
receiver must be programmed to check the same
format. (normal default condition)
Logic 1 = EVEN Parity is generated by forcing an even
the number of logic 1’s in the transmitted. The receiver
must be programmed to check the same format.
LCR BIT-5:
If the parity bit is enabled, LCR BIT-5 selects the
forced parity format.
BIT-2
0
1
1
Word length
5,6,7,8
6,7,8
5
(Bit time(s))
Stop bit
length
1-1/2
1
2