FDD16AN08A0_F085 Fairchild Semiconductor, FDD16AN08A0_F085 Datasheet - Page 8

• Manufacturer Part Number: FDD16AN08A0_F085
• Description: MOSFET N-CH 75V 50A DPAK
• Manufacturer: Fairchild Semiconductor
• Series: UltraFET™r

Specifications of FDD16AN08A0_F085

• Fet Type: MOSFET N-Channel, Metal Oxide
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 16 mOhm @ 50A, 10V
• Drain To Source Voltage (vdss): 75V
• Current - Continuous Drain (id) @ 25° C: 9A
• Vgs(th) (max) @ Id: 4V @ 250µA
• Gate Charge (qg) @ Vgs: 47nC @ 10V
• Input Capacitance (ciss) @ Vds: 1874pF @ 25V
• Power - Max: 135W
• Mounting Type: Surface Mount
• Package / Case: TO-252-3, DPak (2 Leads + Tab), SC-63
• Configuration: Single
• Transistor Polarity: N-Channel
• Resistance Drain-source Rds (on): 0.016 Ohms
• Drain-source Breakdown Voltage: 75 V
• Gate-source Breakdown Voltage: +/- 20 V
• Continuous Drain Current: 50 A
• Power Dissipation: 135 W
• Maximum Operating Temperature: + 175 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 55 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FDD16AN08A0_F085 Rev. A1
PSPICE Electrical Model
.SUBCKT FDD16AN08A0 2 1 3 ; rev March 2002
Ca 12 8 6.8e-10
Cb 15 14 8.9e-10
Cin 6 8 1.8e-9
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
Ebreak 11 7 17 18 80.00
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
Lgate 1 9 4.81e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 4.63e-9
RLgate 1 9 48.1
RLdrain 2 5 10
RLsource 3 7 46.3
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 2e-3
Rgate 9 20 3.9
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 7e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*200),3))}
.MODEL DbodyMOD D (IS=2.4E-11 N=1.08 RS=3.6e-3 TRS1=2.2e-3 TRS2=2.5e-9
+ CJO=1.2e-9 M=5.4e-1 TT=1.70e-8 XTI=3.9)
.MODEL DbreakMOD D (RS=1.5e-1 TRS1=1e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=0.5e-9 IS=1e-30 N=10 M=0.5)
.MODEL MmedMOD NMOS (VTO=3.65 KP=3 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=3.9)
.MODEL MstroMOD NMOS (VTO=4.1 KP=67 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=3.05 KP=0.06 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=39 RS=0.1)
.MODEL RbreakMOD RES (TC1=0.9e-3 TC2=-5e-7)
.MODEL RdrainMOD RES (TC1=2.5e-2 TC2=6.2e-5)
.MODEL RSLCMOD RES (TC1=1e-3 TC2=1e-5)
.MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-5.3e-3 TC2=-1.3e-5)
.MODEL RvtempMOD RES (TC1=-2.7e-3 TC2=1e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-1.5)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1 VOFF=0.5)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.5 VOFF=-1)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
GATE
1
RLGATE
LGATE
9
RGATE
CA
12
20
EVTEMP
+
S1A
S1B
ESG
18
22
EGS
13
8
+
-
-
13
6
8
10
+
+
-
-
14
13
8
6
8
6
RSLC2
S2A
S2B
DPLCAP
EVTHRES
+
EDS
19
8
15
CB
CIN
-
+
-
5
8
51
5
5
+
-
MSTRO
14
51
21
RDRAIN
RSLC1
50
ESLC
16
8
MMED
8
EBREAK
IT
DBREAK
RSOURCE
MWEAK
17
RVTHRES
RBREAK
11
+
-
17
18
7
+
18
-
22
RVTEMP
19
RLSOURCE
DBODY
LSOURCE
VBAT
RLDRAIN
www.fairchildsemi.com
LDRAIN
SOURCE
DRAIN
2
3