XC3S1400AN-4FG676I Xilinx Inc, XC3S1400AN-4FG676I Datasheet - Page 29
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XC3S1400AN-4FG676I
Manufacturer Part Number
XC3S1400AN-4FG676I
Description
IC FPGA SPARTAN 3AN 676FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr
Datasheet
1.XC3S50AN-4TQG144C.pdf
(123 pages)
Specifications of XC3S1400AN-4FG676I
Number Of Logic Elements/cells
25344
Number Of Labs/clbs
2816
Total Ram Bits
589824
Number Of I /o
502
Number Of Gates
1400000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
676-BBGA
Package
676FBGA
Family Name
Spartan®-3AN
Device Logic Units
25344
Device System Gates
1400000
Maximum Internal Frequency
667 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
502
Ram Bits
589824
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S1400AN-4FG676I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Table 23: Setup and Hold Times for the IOB Input Path (Cont’d)
Table 24: Sample Window (Source Synchronous)
DS557 (v4.1) April 1, 2011
Product Specification
Notes:
1.
2.
3.
T
Set/Reset Pulse Width
T
Symbol
T
IOICKPD
RPW_IOB
SAMP
Symbol
The numbers in this table are tested using the methodology presented in
Table 10
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the
appropriate Input adjustment from
These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract
the appropriate Input adjustment from
edge.
Setup and hold
capture window of
an IOB flip-flop.
and
Description
Time from the active transition at the
ICLK input of the Input Flip-Flop (IFF)
to the point where data must be held
at the Input pin. The Input Delay is
programmed.
Minimum pulse width to SR control
input on IOB
Table
13.
Description
The input capture sample window value is highly specific to a particular application, device,
package, I/O standard, I/O placement, DCM usage, and clock buffer. Please consult the
appropriate Xilinx Answer Record for application-specific values.
• Answer Record
Table
Table
26.
26. When the hold time is negative, it is possible to change the data before the clock’s active
30879
LVCMOS25
Conditions
www.xilinx.com
Spartan-3AN FPGA Family: DC and Switching Characteristics
–
(3)
Table 30
Maximum
DELAY_
VALUE
IFD_
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
–
and are based on the operating conditions set forth in
XC3S400AN
XC3S700AN
XC3S1400AN
All
Device
–1.12
–1.70
–2.08
–2.38
–2.23
–2.69
–3.08
–3.35
–1.67
–2.27
–2.59
–2.92
–2.89
–3.22
–3.52
–3.81
–1.60
–2.06
–2.46
–2.86
–2.88
–3.24
–3.55
–3.89
1.33
Min
Speed Grade
-5
–1.12
–1.70
–2.08
–2.38
–2.23
–2.69
–3.08
–3.35
–1.67
–2.27
–2.59
–2.92
–2.89
–3.22
–3.52
–3.81
–1.60
–2.06
–2.46
–2.86
–2.88
–3.24
–3.55
–3.89
1.61
Min
-4
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
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