XC3S1400AN-4FG676I Xilinx Inc, XC3S1400AN-4FG676I Datasheet - Page 47
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XC3S1400AN-4FG676I
Manufacturer Part Number
XC3S1400AN-4FG676I
Description
IC FPGA SPARTAN 3AN 676FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr
Datasheet
1.XC3S50AN-4TQG144C.pdf
(123 pages)
Specifications of XC3S1400AN-4FG676I
Number Of Logic Elements/cells
25344
Number Of Labs/clbs
2816
Total Ram Bits
589824
Number Of I /o
502
Number Of Gates
1400000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
676-BBGA
Package
676FBGA
Family Name
Spartan®-3AN
Device Logic Units
25344
Device System Gates
1400000
Maximum Internal Frequency
667 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
502
Ram Bits
589824
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S1400AN-4FG676I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Configurable Logic Block (CLB) Timing
Table 33: CLB (SLICEM) Timing
DS557 (v4.1) April 1, 2011
Product Specification
Notes:
1.
Clock-to-Output Times
T
Setup Times
T
T
Hold Times
T
T
Clock Timing
T
T
F
Propagation Times
T
Set/Reset Pulse Width
T
AS
AH
CKO
DICK
CKDI
CH
CL
TOG
ILO
RPW_CLB
The numbers in this table are based on the operating conditions set forth in
Symbol
When reading from the FFX (FFY) Flip-Flop, the time
from the active transition at the CLK input to data
appearing at the XQ (YQ) output
Time from the setup of data at the F or G input to the
active transition at the CLK input of the CLB
Time from the setup of data at the BX or BY input to
the active transition at the CLK input of the CLB
Time from the active transition at the CLK input to the
point where data is last held at the F or G input
Time from the active transition at the CLK input to the
point where data is last held at the BX or BY input
The High pulse width of the CLB’s CLK signal
The Low pulse width of the CLK signal
Toggle frequency (for export control)
The time it takes for data to travel from the CLB’s F
(G) input to the X (Y) output
The minimum allowable pulse width, High or Low, to
the CLB’s SR input
Description
www.xilinx.com
Spartan-3AN FPGA Family: DC and Switching Characteristics
Table
0.63
0.18
1.58
0.63
1.33
Min
–
0
0
0
–
10.
-5
Max
0.60
0.62
770
Speed Grade
–
–
–
–
–
–
–
0.36
1.88
0.75
0.75
1.61
Min
–
0
0
0
–
-4
Max
0.68
0.71
667
–
–
–
–
–
–
–
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
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