XC3S1400AN-4FG676I Xilinx Inc, XC3S1400AN-4FG676I Datasheet - Page 78
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XC3S1400AN-4FG676I
Manufacturer Part Number
XC3S1400AN-4FG676I
Description
IC FPGA SPARTAN 3AN 676FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr
Datasheet
1.XC3S50AN-4TQG144C.pdf
(123 pages)
Specifications of XC3S1400AN-4FG676I
Number Of Logic Elements/cells
25344
Number Of Labs/clbs
2816
Total Ram Bits
589824
Number Of I /o
502
Number Of Gates
1400000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
676-BBGA
Package
676FBGA
Family Name
Spartan®-3AN
Device Logic Units
25344
Device System Gates
1400000
Maximum Internal Frequency
667 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
502
Ram Bits
589824
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S1400AN-4FG676I
Manufacturer:
Xilinx Inc
Quantity:
10 000
TQG144 Footprint
Note:
X-Ref Target - Figure 19
DS557 (v4.1) April 1, 2011
Product Specification
42
2
2
0
2
IO_L04N_3/VREF_3 11
IO_L05N_3/LHCLK1
IO_L06N_3/LHCLK3
IO_L07N_3/LHCLK5
IO_L08N_3/LHCLK7
IO_L05P_3/LHCLK0
IO_L06P_3/LHCLK2
IO_L07P_3/LHCLK4
IO_L08P_3/LHCLK6
IP_L13N_3/VREF_3 35
Pin 1 indicator in top-left corner and logo orientation.
I/O: Unrestricted, general-purpose
user I/O
INPUT: Unrestricted,
general-purpose input pin
CONFIG: Dedicated configuration
pins
N.C.: Not connected
SUSPEND: Dedicated SUSPEND
and dual-purpose AWAKE Power
Management pins
IO_L09N_3 25
IO_L02P_3
IO_L01P_3
IO_L02N_3
IO_L01N_3
IO_L03P_3
IO_L03N_3
IO_L04P_3 10
IO_L09P_3 24
IO_L10P_3 27
IO_L11P_3 28
IO_L10N_3 29
IO_L11N_3 30
IO_L12P_3 31
IO_L12N_3 32
IP_L13P_3 33
VCCAUX 36
VCCO_3 14
VCCO_3 23
VCCINT
GND
GND
GND
GND
TMS
TDI
12
13
15
16
17
18
19
20
21
22
26
34
1
2
3
4
5
6
7
8
9
Figure 19: XC3S50AN FPGA in TQG144 Package Footprint (Top View)
X
25
30
13
4
DUAL: Configuration pins, then
possible user I/O
CLK: User I/O, input, or global
buffer input
JTAG: Dedicated JTAG port pins
GND: Ground
www.xilinx.com
Bank 0
Bank 2
Spartan-3AN FPGA Family: Pinout Descriptions
8
8
4
4
VREF: User I/O or input voltage
reference for bank
VCCO: Output voltage supply for
bank
VCCINT: Internal core supply
voltage (+1.2V)
VCCAUX: Auxiliary supply voltage
108 VCCAUX
107
106
105 IO_L11N_1
104 IO_L10N_1
103 IO_L11P_1
102 IO_L10P_1
101 IO_L09N_1
100
99 IO_L09P_1
98 IO_L08N_1
97 IP_1/VREF_1
96 IO_L08P_1
95 VCCO_1
94
93
92
91
90
89
88
87
86 VCCO_1
85
84 IO_L03N_1
83
82 IO_L03P_1
81
80 IP_1/VREF_1
79 IO_1
78 IO_L01N_1/LDC2
77 IO_L02N_1/LDC0
76 IO_L01P_1/HDC
75 IO_L02P_1/LDC1
74 SUSPEND
73 DONE
TDO
GND
GND
VCCINT
IO_L07N_1/RHCLK7
IO_L06N_1/RHCLK5
IO_L07P_1/RHCLK6
IO_L06P_1/RHCLK4
GND
IO_L05N_1/RHCLK3
IO_L05P_1/RHCLK2
IO_L04N_1/RHCLK1
IO_L04P_1/RHCLK0
GND
DS529-4_10_031207
78