ATTINY167-SU Atmel, ATTINY167-SU Datasheet - Page 12

• Manufacturer Part Number: ATTINY167-SU
• Description: IC MCU AVR 16K FLASH 20SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY167-SU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (0.300", 7.50mm Width)
• Core: AVR8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12
Mnemonics
BREAK
MOVW
SLEEP
SWAP
BSET
BCLR
PUSH
WDR
ROR
MOV
SPM
NOP
ROL
ASR
SEC
CLC
SEN
CLN
SES
SEV
SEH
CLH
LDD
LDD
STD
STD
LPM
LPM
LPM
OUT
POP
LSR
BST
BLD
SEZ
CLZ
CLS
CLV
SET
CLT
LDS
STS
SEI
CLI
LDI
LD
LD
LD
LD
LD
LD
LD
LD
LD
ST
ST
ST
ST
ST
ST
ST
ST
ST
IN
ATtiny87/ATtiny167
Operands
Rd, Z+q
Rd,Y+q
Rd, X+
Rd, - X
Rd, Y+
Rd, - Y
Rd, Z+
Y+q,Rr
Z+q,Rr
Rd, Z+
Rd, Rr
Rd, Rr
Rd, -Z
X+, Rr
- X, Rr
Y+, Rr
Z+, Rr
- Y, Rr
Rd, b
Rd, K
Rd, X
Rd, Y
Rd, Z
-Z, Rr
Rd, Z
Rd, P
Rd, k
X, Rr
Z, Rr
Rr, b
Y, Rr
k, Rr
P, Rr
Rd
Rd
Rd
Rd
Rd
Rd
Rr
s
s
Load Program Memory and Post-Inc
Clear Twos Complement Overflow
Set Twos Complement Overflow.
Load Indirect with Displacement
Load Indirect with Displacement
Store Indirect with Displacement
Store Indirect with Displacement
Clear Half Carry Flag in SREG
Set Half Carry Flag in SREG
Rotate Right Through Carry
Bit Store from Register to T
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Rotate Left Through Carry
Bit load from T to Register
Move Between Registers
Pop Register from Stack
Load Direct from SRAM
Global Interrupt Disable
Store Program Memory
Push Register on Stack
Global Interrupt Enable
Load Program Memory
Load Program Memory
Clear Signed Test Flag
Store Direct to SRAM
Arithmetic Shift Right
Set Signed Test Flag
Copy Register Word
Clear Negative Flag
DATA TRANSFER INSTRUCTIONS
Description
Logical Shift Right
Set Negative Flag
Clear T in SREG
Watchdog Reset
Load Immediate
Clear Zero Flag
MCU CONTROL INSTRUCTIONS
Set T in SREG
Swap Nibbles
Set Zero Flag
Store Indirect
Store Indirect
Store Indirect
No Operation
Load Indirect
Load Indirect
Load Indirect
Clear Carry
Flag Clear
Set Carry
Flag Set
Out Port
In Port
Sleep
Break
(see specific descr. for Sleep function)
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
(see specific descr. for WDR/timer)
Rd(n) ← Rd(n+1), Rd(7) ← 0
Rd(n) ← Rd(n+1), n=0..6
For On-chip Debug Only
Rd ← (X), X ← X + 1
Rd ← (Y), Y ← Y + 1
Rd+1:Rd ← Rr+1:Rr
X ← X - 1, Rd ← (X)
Y ← Y - 1, Rd ← (Y)
(X) ← Rr, X ← X + 1
(Y) ← Rr, Y ← Y + 1
Z ← Z - 1, Rd ← (Z)
X ← X - 1, (X) ← Rr
Y ← Y - 1, (Y) ← Rr
(Z) ← Rr, Z ← Z + 1
Rd ← (Z), Z ← Z+1
Z ← Z - 1, (Z) ← Rr
Rd ← (Z), Z ← Z+1
Operation
SREG(s) ← 1
SREG(s) ← 0
Rd ← STACK
Rd ← (Y + q)
Rd ← (Z + q)
STACK ← Rr
(Y + q) ← Rr
(Z + q) ← Rr
(Z) ← R1:R0
Rd(b) ← T
T ← Rr(b)
Rd ← (X)
Rd ← (Y)
Rd ← (Z)
Rd ← (k)
R0 ← (Z)
Rd ← (Z)
(X) ← Rr
(Y) ← Rr
Rd ← Rr
Rd ← K
(Z) ← Rr
(k) ← Rr
Rd ← P
P ← Rr
C ← 1
C ← 0
N ← 1
N ← 0
Z ← 1
Z ← 0
S ← 1
S ← 0
V ← 1
V ← 0
T ← 1
T ← 0
H ← 1
H ← 0
I ← 1
I ← 0
Flags
SREG(s)
SREG(s)
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
C
C
N
N
H
H
T
Z
Z
S
S
V
V
T
T
I
I
8265BS–AVR–09/10
#Clock
N/A
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
1
1
2
2
1
1
1
-