AT89LP52-20MU Atmel, AT89LP52-20MU Datasheet - Page 14

• Manufacturer Part Number: AT89LP52-20MU
• Description: IC MCU 8051 8K FLASH SPI 44VQFN
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP52-20MU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-VFQFN Exposed Pad
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: Serial
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

3.3.2
3.3.2.1
14
AT89LP51/52 - Preliminary
FDATA
Write Protocol
Some internal data memory spaces are mapped into portions of the XDATA address space. In
this case the lower address ranges will access internal resources instead of external memory.
Addresses above the range implemented internally will default to XDATA. The AT89LP51/52
supports up to 63.75K or 56K bytes of external memory when using the internally mapped mem-
ories. Setting the EXRAM bit (AUXR.1) to one will force all MOVX instructions to access the
entire 64KB XDATA regardless of their address (See
page
Figure 3-6.
The Flash Data Memory is a portion of the external memory space implemented as an internal
nonvolatile data memory. Flash Data Memory is enabled by setting the DMEN bit (MEMCON.3)
to one. When IAP = 0 and DMEN = 1, the Flash Data Memory is mapped into the FDATA space,
at the bottom of the external memory address space, from 0000H to 00FFH. (See
MOVX instructions to this address range will access the internal nonvolatile memory. FDATA is
not accessible while DMEN = 0. FDATA can be accessed only by 16-bit (MOVX @DPTR)
addresses. MOVX @Ri instructions to the FDATA address range will access external memory.
Addresses above the FDATA range are mapped to XDATA.
The FDATA address space accesses an internal nonvolatile data memory. This address space
can be read just like EDATA by issuing a MOVX A,@DPTR; however, writes to FDATA require a
more complex protocol and take several milliseconds to complete.
For internal execution the AT89LP51/52 uses an idle-while-write architecture where the CPU is
placed in an idle state while the write occurs. When the write completes, the CPU will continue
executing with the instruction after the MOVX @DPTR,A instruction that started the write. All
0000
FFFF
19).
(XDATA: 64KB)
External Data
EXRAM = 1 or
External Data Memory Map
DMEN = 0
IAP = 0
0100
00FF
FFFF
(XDATA: 63.75KB)
External Data
(FDATA: 256)
EXRAM = 0
Flash Data
DMEN = 1
IAP = 0
“AUXR – Auxiliary Control Register” on
2000
FFFF
1FFF
Flash Program
(XDATA: 56KB)
External Data
(CODE: 8KB)
EXRAM = 0
DMEN = x
IAP = 1
3709B–MICRO–12/10
Figure
3-6).