AT89LP52-20MU Atmel, AT89LP52-20MU Datasheet - Page 37

• Manufacturer Part Number: AT89LP52-20MU
• Description: IC MCU 8051 8K FLASH SPI 44VQFN
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP52-20MU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-VFQFN Exposed Pad
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: Serial
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

9.1
3709B–MICRO–12/10
Interrupt Response Time
vectored to. The Timer 2 Interrupt is generated by a logic OR of bits TF2 and EXF2 in register
T2CON. Neither of these flags is cleared by hardware when the CPU vectors to the service rou-
tine. The service routine normally must determine whether TF2 or EXF2 generated the interrupt
and that bit must be cleared by software.
The Serial Port Interrupt is generated by the logic OR of RI and TI in SCON. Neither of these
flags is cleared by hardware when the CPU vectors to the service routine. The service routine
normally must determine whether RI or TI generated the interrupt and that bit must be cleared by
software.
All of the bits that generate interrupts can be set or cleared by software, with the same result as
though they had been set or cleared by hardware. That is, interrupts can be generated and
pending interrupts can be canceled in software.
Table 9-1.
The interrupt flags may be set by their hardware in any clock cycle. The interrupt controller polls
the flags in the last clock cycle of the instruction in progress. If one of the flags was set in the
preceding cycle, the polling cycle will find it and the interrupt system will generate an LCALL to
the appropriate service routine as the next instruction, provided that the interrupt is not blocked
by any of the following conditions: an interrupt of equal or higher priority level is already in prog-
ress; the instruction in progress is RETI or any write to the IE, IP or IPH registers; the CPU is
currently forced into idle by an IAP or FDATA write. Each of these conditions will block the gen-
eration of the LCALL to the interrupt service routine. The second condition ensures that if the
instruction in progress is RETI or any access to IE, IP or IPH, then at least one more instruction
will be executed before any interrupt is vectored to. The polling cycle is repeated at the last cycle
of each instruction, and the values polled are the values that were present at the previous clock
cycle. If an active interrupt flag is not being serviced because of one of the above conditions and
is no longer active when the blocking condition is removed, the denied interrupt will not be ser-
viced. In other words, the fact that the interrupt flag was once active but not serviced is not
remembered. Every polling cycle is new.
If a request is active and conditions are met for it to be acknowledged, a hardware subroutine
call to the requested service routine will be the next instruction executed. The call itself takes
four cycles. Thus, a minimum of five complete clock cycles elapsed between activation of an
interrupt request and the beginning of execution of the first instruction of the service routine. A
longer response time results if the request is blocked by one of the previously listed conditions. If
an interrupt of equal or higher priority level is already in progress, the additional wait time
depends on the nature of the other interrupt's service routine. If the instruction in progress is not
in its final clock cycle, the additional wait time cannot be more than 4 cycles, since the longest
Interrupt
System Reset
External Interrupt 0
Timer 0 Overflow
External Interrupt 1
Timer 1 Overflow
Serial Port Interrupt
Timer 2 Interrupt
Interrupt Vector Addresses
Source
RST or POR or BOD
IE0
TF0
IE1
TF1
RI or TI
TF2 or EXF2
AT89LP51/52 - Preliminary
Vector Address
000BH
001BH
002BH
0000H
0003H
0013H
0023H
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