ATMEGA32A-AN Atmel, ATMEGA32A-AN Datasheet - Page 183
ATMEGA32A-AN
Manufacturer Part Number
ATMEGA32A-AN
Description
IC MCU AVR 32K FLASH 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA32A-MU.pdf
(353 pages)
Specifications of ATMEGA32A-AN
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
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20.5.1
20.5.2
8155C–AVR–02/11
SCL and SDA Pins
Bit Rate Generator Unit
Figure 20-9. Overview of the TWI Module
These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a
slew-rate limiter in order to conform to the TWI specification. The input stages contain a spike
suppression unit removing spikes shorter than 50 ns. Note that the internal pullups in the AVR
pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins, as
explained in the I/O Port section. The internal pull-ups can in some systems eliminate the need
for external ones.
This unit controls the period of SCL when operating in a Master mode. The SCL period is con-
trolled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status
Register (TWSR). Slave operation does not depend on Bit Rate or Prescaler settings, but the
CPU clock frequency in the slave must be at least 16 times higher than the SCL frequency. Note
that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock
period. The SCL frequency is generated according to the following equation:
Note:
• TWBR = Value of the TWI Bit Rate Register
• TWPS = Value of the prescaler bits in the TWI Status Register
Pull-up resistor values should be selected according to the SCL frequency and the capacitive bus
line load. See
Slew-rate
Address Match Unit
Arbitration detection
Control
START / STOP
Address Comparator
Address Register
Control
SCL
(TWAR)
Table 27-2 on page 300
Spike
Filter
Bus Interface Unit
SCL frequency
Spike Suppression
Address/Data Shift
Register (TWDR)
Slew-rate
Control
for value of pull-up resistor.
=
SDA
Status Register
---------------------------------------------------------- -
16
CPU Clock frequency
Ack
Spike
Filter
(TWSR)
+
2(TWBR) 4
State Machine and
Control Unit
Status control
⋅
TWPS
Control Register
Bit Rate Generator
(TWCR)
Bit Rate Register
Prescaler
(TWBR)
ATmega32A
TWI Unit
183
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