ATMEGA64A-MN Atmel, ATMEGA64A-MN Datasheet - Page 293

• Manufacturer Part Number: ATMEGA64A-MN
• Description: IC MCU AVR 64K FLASH 8QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64A-MN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

26.9
26.9.1
8160C–AVR–07/09
Register Description
SPMCSR – Store Program Memory Control Register
Table 26-8.
Note:
The Store Program Memory Control Register contains the control bits needed to control the Boot
Loader operations.
• Bit 7 – SPMIE: SPM Interrupt Enable
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM
ready interrupt will be enabled. The SPM ready interrupt will be executed as long as the SPMEN
bit in the SPMCSR Register is cleared.
• Bit 6 – RWWSB: Read-While-Write Section Busy
When a Self-programming (Page Erase or Page Write) operation to the RWW section is initi-
ated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section
cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a
Self-programming operation is completed. Alternatively the RWWSB bit will automatically be
cleared if a page load operation is initiated.
• Bit 5 – Res: Reserved Bit
This bit is a reserved bit in the ATmega64A and always read as zero.
Bit
(0x68)
Read/Write
Initial Value
PCMSB
PAGEMSB
ZPCMSB
ZPAGEMSB
PCPAGE
PCWORD
Variable
1. Z0: should be zero for all SPM commands, byte select for the LPM instruction.
2. See
Z-pointer during Self-programming.
SPMIE
R/W
Explanation of Different Variables Used in
pointer
7
0
“Addressing the Flash During Self-programming” on page 286
PC[14:7]
PC[6:0]
14
6
RWWSB
(1)(2)
R
6
0
Corresponding
Z-value
R
Z15:Z8
5
–
0
Z7:Z1
Z15
Z7
RWWSRE
R/W
4
0
Description
Most significant bit in the Program Counter. (The
Program Counter is 15 bits PC[14:0]).
Most significant bit which is used to address the
words within one page (128 words in a page
requires seven bits PC [6:0]).
Bit in Z-register that is mapped to PCMSB. Because
Z0 is not used, the ZPCMSB equals PCMSB + 1.
Bit in Z-register that is mapped to PAGEMSB.
Because Z0 is not used, the ZPAGEMSB equals
PAGEMSB + 1.
Program Counter page address: Page select, for
Page Erase and Page Write
filling temporary buffer (must be zero during Page
Write operation)
Program Counter word address: Word select, for
BLBSET
R/W
3
0
Figure 26-3
PGWRT
R/W
2
0
PGERS
and the Mapping to the Z-
R/W
1
0
for details about the use of
ATmega64A
SPMEN
R/W
0
0
SPMCSR
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