ATMEGA64A-MN Atmel, ATMEGA64A-MN Datasheet - Page 323
ATMEGA64A-MN
Manufacturer Part Number
ATMEGA64A-MN
Description
IC MCU AVR 64K FLASH 8QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA64A-AU.pdf
(392 pages)
Specifications of ATMEGA64A-MN
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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27.9.12
27.9.13
8160C–AVR–07/09
Virtual Flash Page Read Register
Programming Algorithm
Figure 27-16. Virtual Flash Page Load Register
The Virtual Flash Page Read Register is a virtual scan chain with length equal to the number of
bits in one Flash page plus eight. Internally the Shift Register is 8-bit, and the data are automati-
cally transferred from the Flash data page byte-by-byte. The first eight cycles are used to
transfer the first byte to the internal Shift Register, and the bits that are shifted out during these
eight cycles should be ignored. Following this initialization, data are shifted out starting with the
LSB of the first instruction in the page and ending with the MSB of the last instruction in the
page. This provides an efficient way to read one full Flash page to verify programming.
Figure 27-17. Virtual Flash Page Read Register
All references below of type “1a”, “1b”, and so on, refer to
TDO
TDO
TDI
TDI
D
D
A
T
A
A
T
A
Machine
Machine
State
State
STROBES
ADDRESS
STROBES
ADDRESS
Table
EEPROM
EEPROM
Lock Bits
Lock Bits
Fuses
Fuses
Flash
Flash
27-16.
ATmega64A
323
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