ATMEGA64A-MN Atmel, ATMEGA64A-MN Datasheet - Page 96
ATMEGA64A-MN
Manufacturer Part Number
ATMEGA64A-MN
Description
IC MCU AVR 64K FLASH 8QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA64A-AU.pdf
(392 pages)
Specifications of ATMEGA64A-MN
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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14.6
8160C–AVR–07/09
Compare Match Output Unit
(FOC0) strobe bit in Normal mode. The OC0 Register keeps its value even when changing
between waveform generation modes.
Be aware that the COM01:0 bits are not double buffered together with the compare value.
Changing the COM01:0 bits will take effect immediately.
The Compare Output mode (COM01:0) bits have two functions. The Waveform Generator uses
the COM01:0 bits for defining the Output Compare (OC0) state at the next Compare Match.
Also, the COM01:0 bits control the OC0 pin output source.
matic of the logic affected by the COM01:0 bit setting. The I/O Registers, I/O bits, and I/O pins in
the figure are shown in bold. Only the parts of the general I/O port control registers (DDR and
PORT) that are affected by the COM01:0 bits are shown. When referring to the OC0 state, the
reference is for the internal OC0 Register, not the OC0 pin.
Figure 14-4. Compare Match Output Unit, Schematic
The general I/O port function is overridden by the Output Compare (OC0) from the Waveform
Generator if either of the COM01:0 bits are set. However, the OC0 pin direction (input or output)
is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Regis-
ter bit for the OC0 pin (DDR_OC0) must be set as output before the OC0 value is visible on the
pin. The port override function is independent of the Waveform Generation mode.
The design of the Output Compare pin logic allows initialization of the OC0 state before the out-
put is enabled. Note that some COM01:0 bit settings are reserved for certain modes of
operation.
COMn1
COMn0
FOCn
clk
I/O
See “Register Description” on page 106.
Waveform
Generator
D
D
D
PORT
DDR
OCn
Q
Q
Q
Figure 14-4
1
0
shows a simplified sche-
ATmega64A
OCn
Pin
96
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