PK10N512VLK100 Freescale Semiconductor, PK10N512VLK100 Datasheet - Page 57
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
PK10N512VLK100
Manufacturer Part Number
PK10N512VLK100
Description
IC ARM CORTEX MCU 512K 80-LQFP
Manufacturer
Freescale Semiconductor
Series
Kinetisr
Datasheet
1.PK10N512VLK100.pdf
(64 pages)
Specifications of PK10N512VLK100
Core Processor
ARM Cortex-M4
Core Size
32-Bit
Speed
100MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SDHC, SPI, UART/USART
Peripherals
DMA, I²S, LVD, POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.71 V ~ 3.6 V
Data Converters
A/D 27x16b, D/A 1x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
80-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PK10N512VLK100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
8.1 K10 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
Freescale Semiconductor, Inc.
MAP
BGA
81
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
LQF
80
10
11
12
13
14
15
16
17
18
19
P
1
2
3
4
5
6
7
8
9
PTE0
PTE1
PTE2
PTE3
PTE4
PTE5
VDD
VSS
PTE16
PTE17
PTE18
PTE19
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
VDDA
VREFH
VREFL
Pin Name
The 81-pin ballmap assignments are currently being developed.
The • in the entries in this package column indicate which
signals are present on the package.
ADC1_SE4
a
ADC1_SE5
a
ADC1_SE6
a
ADC1_SE7
a
DISABLED
DISABLED
VDD
VSS
ADC0_SE4
a
ADC0_SE5
a
ADC0_SE6
a
ADC0_SE7
a
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
VDDA
VREFH
VREFL
Default
K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
ADC1_SE4
a
ADC1_SE5
a
ADC1_SE6
a
ADC1_SE7
a
VDD
VSS
ADC0_SE4
a
ADC0_SE5
a
ADC0_SE6
a
ADC0_SE7
a
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
VDDA
VREFH
VREFL
ALT0
PTE0
PTE1
PTE2
PTE3
PTE4
PTE5
PTE16
PTE17
PTE18
PTE19
ALT1
SPI1_PCS1 UART1_TX
SPI1_SOUT UART1_RX SDHC0_D0
SPI1_SCK
SPI1_SIN
SPI1_PCS0 UART3_TX
SPI1_PCS2 UART3_RX SDHC0_D2
SPI0_PCS0 UART2_TX
SPI0_SCK
SPI0_SOUT UART2_CT
SPI0_SIN
ALT2
Preliminary
NOTE
UART1_CT
S_b
UART1_RT
S_b
UART2_RX FTM_CLKIN
S_b
UART2_RT
S_b
ALT3
SDHC0_D1
SDHC0_DC
LK
SDHC0_CM
D
SDHC0_D3
FTM_CLKIN
0
1
I2C0_SDA
I2C0_SCL
ALT4
ALT5
I2C1_SDA
I2C1_SCL
FTM0_FLT3
LPT00_ALT
3
ALT6
ALT7
EzPort
Pinout
57