PK10N512VMD100 Freescale Semiconductor, PK10N512VMD100 Datasheet - Page 23

• Manufacturer Part Number: PK10N512VMD100
• Description: IC ARM CORTEX MCU 512K 144-MAP
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr

Specifications of PK10N512VMD100

• Core Processor: ARM Cortex-M4
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SDHC, SPI, UART/USART
• Peripherals: DMA, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 37x16b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LBGA
• Processor Series: Kinetis
• Core: ARM Cortex M4
• Data Ram Size: 128 KB
• Interface Type: UART, SPI, I2C, I2S, CAN
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 104
• Operating Supply Voltage: 1.71 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor, Inc.
Symbol
J10
J11
J12
J13
J14
TCLK (input)
TCLK
Data inputs
Data outputs
Data outputs
Data outputs
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
TCLK low to TDO high-Z
TRST assert time
TRST setup time (negation) to TCLK high
Description
Table 12. JTAG full voltage range electricals (continued)
K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Figure 6. Boundary scan (JTAG) timing
Figure 5. Test clock input timing
J4
Preliminary
J3
J7
J8
J7
J2
J4
Peripheral operating requirements and behaviors
J5
Input data valid
Output data valid
Output data valid
J3
Min.
100
1.4
—
—
8
J6
Max.
22.1
22.1
—
—
—
Unit
ns
ns
ns
ns
ns
23