PK10N512VMD100 Freescale Semiconductor, PK10N512VMD100 Datasheet - Page 26

• Manufacturer Part Number: PK10N512VMD100
• Description: IC ARM CORTEX MCU 512K 144-MAP
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr

Specifications of PK10N512VMD100

• Core Processor: ARM Cortex-M4
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SDHC, SPI, UART/USART
• Peripherals: DMA, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 37x16b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LBGA
• Processor Series: Kinetis
• Core: ARM Cortex M4
• Data Ram Size: 128 KB
• Interface Type: UART, SPI, I2C, I2S, CAN
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 104
• Operating Supply Voltage: 1.71 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Peripheral operating requirements and behaviors
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. This specification was obtained at TBD frequency.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
8. Excludes any oscillator currents that are also consuming power while PLL is in operation.
9. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
10. This specification was obtained at internal frequency of TBD.
11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
26
f
dco_t_DMX3
t
Symbol
fll_acquire
J
J
t
J
J
f
pll_lock
mode).
(Δf
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
each PCB and results will vary.
D
acc_pll
pll_ref
cyc_pll
D
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
cyc_fll
acc_fll
f
I
vco
lock
pll
2
unl
dco_t
) over voltage and temperature should be considered.
DCO output
frequency
FLL period jitter
FLL accumulated jitter of DCO output over a 1µs
time window
FLL target frequency acquisition time
VCO operating frequency
PLL operating current
PLL reference frequency range
PLL period jitter
PLL accumulated jitter over 1µs window
Lock entry frequency tolerance
Lock exit frequency tolerance
Lock detector detection time
Description
• PLL @ 96 MHz (f
f
pll_ref
=2MHz, VDIV multiplier=48)
K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Table 13. MCG specifications (continued)
Mid-high range (DRS=10)
High range (DRS=11)
Low range (DRS=00)
osc_hi_1
Mid range (DRS=01)
1464 × f
2197 × f
2929 × f
732 × f
=8MHz,
fll_ref
fll_ref
fll_ref
fll_ref
Preliminary
PLL
± 1.49
± 4.47
48.0
Min.
2.0
—
—
—
—
—
—
—
—
—
—
—
23.99
47.97
71.99
95.98
TBD
TBD
TBD
Typ.
950
400
—
—
—
—
—
—
1075(1/
± 2.98
± 5.97
0.15 +
f
Max.
TBD
TBD
pll_ref
100
4.0
—
—
—
—
—
—
—
1
Freescale Semiconductor, Inc.
)
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ms
µA
ms
ps
ps
ps
ps
%
%
Notes
9,
9,
4,
11
6
6
7
8
10
10
5