DS92LV2412SQE/NOPB National Semiconductor, DS92LV2412SQE/NOPB Datasheet - Page 28

• Manufacturer Part Number: DS92LV2412SQE/NOPB
• Description: IC DESERIALIZER 24BIT 60LLP
• Manufacturer: National Semiconductor

Specifications of DS92LV2412SQE/NOPB

• Function: Deserializer
• Data Rate: 1.2Gbps
• Input Type: CML
• Output Type: LVCMOS
• Number Of Inputs: 1
• Number Of Outputs: 24
• Voltage - Supply: 1.71 V ~ 1.89 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 60-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DS92LV2412SQE/NOPBTR

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Des — OP_LOW — Optional
The OP_LOW feature is used to hold the LVCMOS outputs,
except for the LOCK output, at a LOW state. When the
OP_LOW feature is enabled, the LVCMOS outputs will be
held at logic LOW while LOCK = LOW. The user must toggle
the OP_LOW Set/Reset register bit to release the outputs to
the normal toggling state. Note that the release of the outputs
can only occur when LOCK is HIGH. The OP_LOW strap op-
tion is assigned to the PASS pin, at pin location 42.
Restrictions on other straps:
1.
Other strap options should not be used in order to keep
the data and clock outputs at a true logic LOW state.
FIGURE 25. OP_LOW Manual Set/Reset
FIGURE 24. OP_LOW Auto Set
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2.
Outputs DO[23:0], CO[3:1] and CLKOUT are in TRI-STATE™
before PDB toggles HIGH because the OP-LOW strap value
has not been recognized until the DS92LV2412 powers up.
Figure 24
and automatic reset of OP_LOW set on the falling edge of
LOCK.
OP_LOW and manual reset of OP_LOW set. Note manual
reset of OP_LOW can only occur when LOCK is HIGH.
Other features should be selected through the I2C
register interface.
The OSS_SEL feature is not available when OP_LOW is
enabled.
Figure 25
shows the user controlled release of the OP_LOW
shows the user controlled release of
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