DS92LV2412SQE/NOPB National Semiconductor, DS92LV2412SQE/NOPB Datasheet - Page 7

• Manufacturer Part Number: DS92LV2412SQE/NOPB
• Description: IC DESERIALIZER 24BIT 60LLP
• Manufacturer: National Semiconductor

Specifications of DS92LV2412SQE/NOPB

• Function: Deserializer
• Data Rate: 1.2Gbps
• Input Type: CML
• Output Type: LVCMOS
• Number Of Inputs: 1
• Number Of Outputs: 24
• Voltage - Supply: 1.71 V ~ 1.89 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 60-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DS92LV2412SQE/NOPBTR

Pin Name
LVCMOS Parallel Interface
DO[7:0]
DO[15:8]
DO[23:16]
CO1
CO2
CO3
CLKOUT
LOCK
PASS
DS92LV2412 Deserializer Pin Descriptions
33, 34, 35,
36, 37, 39,
20, 21, 22,
23, 25, 26,
12, 14, 17,
9, 10, 11,
40, 41
27, 28
18, 19
Pin #
32
42
6
8
7
5
O, LVCMOS
O, LVCMOS
O, LVCMOS
O, LVCMOS Control Signal Output
O, LVCMOS Control Signal Output
O, LVCMOS Control Signal Output
O, LVCMOS Pixel Clock Output
O, LVCMOS LOCK Status Output
O, LVCMOS PASS Output (BIST Mode)
I, STRAP,
I, STRAP,
I, STRAP,
I/O, Type
Description
Parallel Interface Data Output Pins
For 8–bit RED Display: DO7 = R7 – MSB, DO0 = R0 – LSB.
In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See
pins are inputs during power-up (See STRAP Inputs).
Parallel Interface Data Output Pins
For 8–bit GREEN Display: DO15 = G7 – MSB, DO8 = G0 – LSB.
In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See
pins are inputs during power-up (See STRAP Inputs).
Parallel Interface Data Input Pins
For 8–bit BLUE Display: DO23 = B7 – MSB, DO16 = B0 – LSB.
In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See
pins are inputs during power-up (See STRAP Inputs).
For Display/Video Application:
CO1 = Data Enable Output
Control signal pulse width must be 3 clocks or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00).
The signal is limited to 2 transitions per 130 clocks regardless of the Control Signal Filter
setting.
In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See
For Display/Video Application:
CO2 = Horizontal Sync Output
Control signal pulse width must be 3 clocks or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00).
The signal is limited to 2 transitions per 130 clocks regardless of the Control Signal Filter
setting.
In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See
For Display/Video Application:
CO3 = Vertical Sync Output
CO3 is different than CO1 and CO2 because it is limited to 1 transition per 130 clock cycles.
Thus, the minimum pulse width allowed is 130 clock cycle wide.
The CONFIG[1:0] pins have no affect on CO3 signal
In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See
In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See
strobe edge set by RFB.
LOCK = 1, PLL is Locked, outputs are active LOCK = 0, PLL is unlocked, DO[23:0], CO1,
CO2, CO3 and CLKOUT output states are controlled by OSS_SEL (See
used as Link Status or to flag when Video Data is active (ON/OFF).
PASS = 1, error free transmission
PASS = 0, one or more errors were detected in the received payload
Route to test point for monitoring, or leave open if unused.
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