DS92LV2412SQE/NOPB National Semiconductor, DS92LV2412SQE/NOPB Datasheet - Page 8

• Manufacturer Part Number: DS92LV2412SQE/NOPB
• Description: IC DESERIALIZER 24BIT 60LLP
• Manufacturer: National Semiconductor

Specifications of DS92LV2412SQE/NOPB

• Function: Deserializer
• Data Rate: 1.2Gbps
• Input Type: CML
• Output Type: LVCMOS
• Number Of Inputs: 1
• Number Of Outputs: 24
• Voltage - Supply: 1.71 V ~ 1.89 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 60-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DS92LV2412SQE/NOPBTR

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Pin Name
Control and Configuration — STRAP PINS
For a High State, use a 10 kΩ pull up to V
power-up and set device configuration. Pin Number listed along with shared data output name in square brackets.
CONFIG[1:0]
LF_MODE
OS_CLKOUT
OS_DATA
OP_LOW
OSS_SEL
RFB
EQ[3:0]
OSC_SEL[2:0] 26 [DO10],
SSC[3:0]
MAP_SEL[1:0]
10 [DO22],
20 [DO15],
21 [DO14],
22 [DO13],
12 [DO20]
11 [DO21]
14 [DO19]
42 [PASS]
17 [DO18]
18 [DO17]
23 [DO12]
27 [DO9],
34 [DO6],
35 [DO5],
36 [DO4],
9 [DO23]
28 [DO8]
37 [DO3]
40[D],
41 [D]
Pin #
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I/O, Type
STRAP
STRAP
STRAP
STRAP
STRAP
STRAP
STRAP
STRAP
STRAP
STRAP
STRAP
DDIO
Description
00: Control Signal Filter DISABLED. Interfaces with DS92LV2411 or DS92LV0411
01: Control Signal Filter ENABLED. Interfaces with DS92LV2411 or DS92LV0411
10: Reverse compatibility mode to interface with the DS90UR241 or DS99R241
11: Reverse compatibility mode to interface with the DS90C241
SSCG Low Frequency Mode
Only required when SSCG is enabled, otherwise LF_MODE condition is a DON’T CARE
(X).
LF_MODE = 1, SSCG in low frequency mode (CLK = 5-20 MHz)
LF_MODE = 0, SSCG in high frequency mode (CLK = 20-50 MHz)
This can also be controlled by I2C register access.
Output CLKOUT Slew Select
OS_CLKOUT = 1, Increased CLKOUT slew rate
OS_CLKOUT = 0, Normal CLKOUT slew rate (default)
This can also be controlled by I2C register access.
Output DO[23:0], CO1, CO2, CO3 Slew Select
OS_DATA = 1, Increased DO slew rate
OS_DATA = 0, Normal DO slew rate (default)
This can also be controlled by I2C register access.
Outputs held LOW when LOCK = 1
NOTE: Do not use any other strap options with this strap function enabled
OP_LOW = 1: all outputs are held LOW during power up until released by programming
OP_LOW release/set register HIGH.
NOTE: Before the device is powered up, the outputs are in TRI-STATE™
See
OP_LOW = 0: all outputs toggle normally as soon as LOCK goes HIGH (default)
This can also be controlled by I2C register access.
Output Sleep State Select
OSS_SEL is used in conjunction with PDB to determine the state of the outputs in Power
Down (Sleep). (See
NOTE: OSS_SEL STRAP CANNOT BE USED IF OP_LOW = 1
This can also be controlled by I2C register access.
Clock Output Strobe Edge Select
RFB = 1, parallel interface data and control signals are strobed on the rising clock edge.
RFB = 0, parallel interface data and control signals are strobed on the falling clock edge.
This can also be controlled by I2C register access.
Receiver Input Equalization
(See
This can also be controlled by I2C register access.
Oscillator Selectl
(See
This can also be controlled by I2C register access.
Spread Spectrum Clock Generation (SSCG) Range Select
(See
This can also be controlled by I2C register access.
Bit mapping reverse compatibility / DS90UR241 Options
Pin or Register Control
Default setting is b'00.
; for a Low State, the IO includes an internal pull down. The STRAP pins are read upon
Figure 24
Table
Table 9
Table 6
5).
and
and
and
Table
Table
Figure 25
Table
8
10).
7).
8).