DS92LV0412SQX/NOPB National Semiconductor, DS92LV0412SQX/NOPB Datasheet - Page 21

• Manufacturer Part Number: DS92LV0412SQX/NOPB
• Description: IC SER/DESER 5-50MHZ 24B 48LLP
• Manufacturer: National Semiconductor

Specifications of DS92LV0412SQX/NOPB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
The DS92LV0411 / DS92LV0412 chipset transmits and re-
ceives 24-bits of data and 3 control signals, formatted as
Channel Link LVDS data, over a single serial CML pair oper-
ating at 140 Mbps to 1.4 Gbps serial line rate. The serial
stream contains an embedded clock, video control signals
and is DC-balance to enhance signal quality and supports AC
coupling.
The Des can attain lock to a data stream without the use of a
separate reference clock source, which simplifies system
complexity and overall cost. The Des also synchronizes to the
Ser regardless of the data pattern, delivering true automatic
“plug and lock” performance. It can lock to the incoming serial
stream without the need of special training patterns or sync
characters. The Des recovers the clock and data by extracting
the embedded clock information, validating and then deseri-
alizing the incoming data stream providing a parallel Channel
Link LVDS bus to the display, ASIC, or FPGA.
The DS92LV0411 / DS92LV0412 chipset can operate with up
to 24 bits of raw data with three slower speed control bits en-
coded within the serial data stream. For applications that
require less the maximum 24 pclk speed bit spaces, the user
will need to ensure that all unused bit spaces or parallel LVDS
channels are set to valid logic states, as all parallel lanes and
27 bit spaces will always be sampled.
Block Diagrams for the chipset are shown at the beginning of
this datasheet.
PARALLEL LVDS DATA TRANSFER
The DS92LV0411/DS92LV0412 can be configured to accept/
transmit 24-bit data with 2 different mapping schemes: The
normal Channel Link LVDS format (MSBs on LVDS channel
3) can be selected by configuring the MAPSEL pin to HIGH.
See Figure 13 for the normal Channel Link LVDS mapping.
An alternate mapping scheme is available (LSBs on LVDS
channel 3) by configuring the MAPSEL pin to LOW. See Fig-
ure 14 for the alternate LVDS mapping. The mapping
schemes can also be selected by register control.
The alternate mapping scheme is useful in some applications
where the receiving system, typically a display, requires that
the LSBs for the 24-bit color data be sent on LVDS channel
3.
SERIAL DATA TRANSFER
The DS92LV0411 transmits a 24–bit word of data in the fol-
lowing format: C1 and C0 represent the embedded clock in
the serial stream. C1 is always HIGH and C0 is always LOW.
b[23:0] contain the scrambled RGB data, plus two additional
bits for encoding overhead. The control signals (VS,HS,DE)
are also encoded within these two additional bits. This coding
scheme is generated by the DS92LV0411 and decoded by
the paring deserializer, such as the DS92LV0412, automati-
cally.
The DS92LV0412 receives a 24 bit word of data in the format
as described above. It also synchronizes to the serializer re-
gardless of the data pattern, delivering true automatic “plug
and lock” performance. it can lock to the incoming serial
stream without the need for special training patterns or sync
characters. The DS92LV0412 recovers the clock and data by
extracting the embedded clock information, validating and
then deserializing the incoming data stream.
21
illustrates the serial stream per PCLK cycle.
OPERATING MODES AND BACKWARD COMPATIBILITY
(CONFIG[1:0])
The DS92LV0411 and DS92LV0412 are backward compati-
ble with previous generations of National Ser/Des. Configu-
ration modes are provided for backwards compatibility with
the DS90C241/DS90C124 and also the DS90UR241/
DS90UR124 and DS99R241/DS99R124 by setting the re-
spective mode with the CONFIG[1:0] pins as shown in
1
Video Control Signal filter feature is enabled or disabled in
Normal mode. Backward compatibility modes are selectable
through the control pins only. The Control Signal Filter can be
selected by pin or through register programming.
BIT MAPPING SELECT
The DS92LV0411 and DS92LV0412 can be configured to ac-
cept the LVDS parallel data with 2 different mapping
schemes: LSBs on RxIN[3] shown in
RxIN[3] shown in
scheme is controlled by MAPSEL pin or by Register.
IMPORTANT NOTE — while the LVDS interface has 28 bits
defined, only 27 bits are recovered by the Ser and sent to the
Des. This supports 24 bit RGB plus the three video control
signals. The 28th bit is not sampled, sent or recovered.
CON
FIG1
CON
FIG1
and
H
H
H
H
L
L
L
L
TABLE 1. DS92LV0411 Configuration Modes
TABLE 2. DS92LV0412 Configuration Modes
Table
FIGURE 19. Channel Link II Serial Stream
CON
FIG0
CON
FIG0
H
H
H
H
L
L
L
L
2. The selection also determine whether the
Mode
Normal Mode, Control
Signal Filter disabled
Normal Mode, Control
Signal Filter enabled
Backwards Compatible
Backwards Compatible
Mode
Normal Mode, Control
Signal Filter disabled
Normal Mode, Control
Signal Filter enabled
Backwards Compatible
Backwards Compatible
Figure
21. The user selects which mapping
Figure 20
Des Device
DS92LV0412,
DS92LV2412
DS92LV0412,
DS92LV2412
DS90UR124,
DS99R124
DS90C124
Des Device
DS92LV0411,
DS92LV2411
DS92LV0411,
DS92LV2411
DS90UR241,
DS99R421
DS90C241
or MSBs on
www.national.com
30125237
Table