DS92LV0412SQX/NOPB National Semiconductor, DS92LV0412SQX/NOPB Datasheet - Page 24

• Manufacturer Part Number: DS92LV0412SQX/NOPB
• Description: IC SER/DESER 5-50MHZ 24B 48LLP
• Manufacturer: National Semiconductor

Specifications of DS92LV0412SQX/NOPB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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POWER SAVING FEATURES
Ser — Power Down Feature (PDB)
The DS92LV0411 has a PDB input pin to ENABLE or POWER
DOWN the device. This pin is controlled by the host and is
used to save power, disabling the link when the display is not
needed. In the POWER DOWN mode, the high-speed driver
outputs are both pulled to VDD and present a 0V VOD state.
Note – in POWER DOWN, the optional Serial Bus Control
Registers are RESET.
Ser — Stop Clock Feature
The DS92LV0411 will enter a low power SLEEP state when
the RxCLKIN is stopped. A STOP condition is detected when
the input clock frequency is less than 3 MHz. The clock should
be held at a static Low or high state. When the RxCLKIN starts
again, the device will then lock to the valid input RxCLKIN and
then transmits the RGB data to the desializer. Note – in STOP
CLOCK SLEEP, the optional Serial Bus Control Registers
values are RETAINED.
1.8V or 3.3V VDDIO Operation
The DS92LV0411 parallel control pin bus can operate with
1.8 V or 3.3 V levels (V
levels will offer a system power savings.
Resistor Value (kΩ)
Open
0.6
1.0
2.0
5.0
TABLE 4. De-Emphasis Resistor Value
FIGURE 23. De-Emph vs. R value
DDIO
) for host compatibility. The 1.8 V
De-Emphasis Setting
Disabled
- 12 dB
- 9 dB
- 6 dB
- 3 dB
30125260
24
OPTIONAL SERIAL BUS CONTROL
Please see the following section on the optional Serial Bus
Control Interface.
OPTIONAL BIST MODE
Please see the following section on the chipset BIST mode
for details.
Deserializer Functional Description
The Des converts a single input serial data stream to a wide
parallel output bus, and also provides a signal check for the
chipset Built In Self Test (BIST) mode. The device can be
configured via external pins and strap pins or through the op-
tional serial control bus. The Des features enhance signal
quality on the link with an integrated equalizer on the serial
input and Channel Link II data encoding which provides ran-
domization, scrambling, and DC balanacing of the data. The
Des includes multiple features to reduce EMI associated with
data transmission. This includes the randomization and
scrambling of the data, the output spread spectrum clock
generation (SSCG) support. The Des features power saving
features with a power down mode, and optional LVCMOS (1.8
V) interface compatibility.
OSCILLATOR OUTPUT — OPTIONAL
The DS92LV0412 provides an optional TxCLKOUT when the
input clock (serial stream) has been lost. This is based on an
internal oscillator. The frequency of the oscillator may be se-
lected. This feature may be controlled by the external pin or
through the registers.
Clock-DATA RECOVERY STATUS FLAG (LOCK),
OUTPUT ENABLE (OEN) and OUTPUT STATE SELECT
(OSS_SEL)
When PDB is driven HIGH, the CDR PLL begins locking to
the serial input, LOCK is LOW and the Channel Link interface
state is determined by the state of the OSS_SEL pin.
After the DS92LV0412 completes its lock sequence to the in-
put serial data, the LOCK output is driven HIGH, indicating
valid data and clock recovered from the serial input is avail-
able on the Channel Link outputs. The TxCLKOUT output is
held at its current state at the change from OSC_CLK (if this
is enabled via OSC_SEL) to the recovered clock (or vice ver-
sa). Note that the Channel Link outputs may be held in an
inactive state (TRI-STATE®) through the use of the Output
Enable pin (OEN).
If there is a loss of clock from the input serial stream, LOCK
is driven LOW and the state of the outputs are based on the
OSS_SEL setting (configuration pin or register).