DS92LV0412SQX/NOPB National Semiconductor, DS92LV0412SQX/NOPB Datasheet - Page 3

• Manufacturer Part Number: DS92LV0412SQX/NOPB
• Description: IC SER/DESER 5-50MHZ 24B 48LLP
• Manufacturer: National Semiconductor

Specifications of DS92LV0412SQX/NOPB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Name
Channel Link Parallel Input Interface
RxIN[3:0]+
RxIN[3:0]-
RxCLKIN+
RxCLKIN-
Control and Configuration
PDB
DS92LV0411 Pin Diagram
DS92LV0411 Pin Descriptions
1, 34, 32, 30,
2, 33, 31, 29
Pin #
28
35
34
23
w/ pull-down
I, LVCMOS
I/O, Type
I, LVDS
I, LVDS
I, LVDS
I, LVDS
Description
True LVDS Data Input
These inputs require an external 100 Ω differential termination for standard LVDS levels.
Inverting LVDS Data Input
These inputs require an external 100 Ω differential termination for standard LVDS levels.
True LVDS Clock Input
These inputs require an external 100 Ω differential termination for standard LVDS levels.
Inverting LVDS Clock Input
These inputs require an external 100 Ω differential termination for standard LVDS levels.
Power-down Mode Input
PDB = 1, Device is enabled (normal operation).
Refer to ”Power Up Requirements and PDB Pin” in the Applications Information Section.
PDB = 0, Device is powered down
When the Device is in the power-down state, the driver outputs (DOUT+/-) are both logic
high, the PLL is shutdown, IDD is minimized. Control Registers are RESET.
DS92LV0411 — Top View
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