LM2512SM/NOPB National Semiconductor, LM2512SM/NOPB Datasheet
LM2512SM/NOPB
Specifications of LM2512SM/NOPB
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LM2512SM/NOPB Summary of contents
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... PCLK (DES dependant the PD* input pins. The LM2512 implements the physical layer of the MPL Level 0 Standard (MPL-0) and a 450 μA I OMS Typical 3 MD Lane Application Diagram - Bridge Chip © 2010 National Semiconductor Corporation 201728 Version 5 Revision 1 LM2512 Features ■ 24-bit RGB Display Interface support up to 640 x 480 VGA formats ■ ...
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Ordering Information NSID Package Type LM2512SM 49L UFBGA, 4.0 X 4.0 X 1.0 mm, 0.5 mm pitch LM2512SN 40L LLP, 6.0 X 6.0 X 0.4 mm, 0.5 mm pitch www.national.com 2 201728 Version 5 Revision 1 Print Date/Time: 2010/01/20 21:11:52 ...
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Pin Descriptions No. Pin Name of Pins MPL SERIAL BUS PINS MD[2: SPI INTERFACE and CONFIGURATION PINS SPI_CSX 1 SPI_SCL 1 SPI_SDA/HS 1 PD* 1 RES1 VIDEO INTERFACE PINS PCLK 1 R[7:0] ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V ) DDA Supply Voltage ( Supply Voltage (V ) DDIO LVCMOS Input/Output Voltage MPL Output Voltage Junction Temperature Storage Temperature ESD Ratings: HBM, 1.5 kΩ, 100 pF EIAJ, 0Ω ...
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Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter PARALLEL BUS TIMING t Set Up Time SET t Hold Time HOLD SERIAL BUS TIMING t Serial Data Valid before Clock DVBC Edge t Serial Data ...
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Recommended Input Timing Requirements (PCLK and SPI) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter PIXEL CLOCK (PCLK) f Pixel Clock Frequency PCLK PCLK Pixel Clock Duty Cycle DC t Transition Time T t Clock Stop ...
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Timing Diagrams 201728 Version 5 Revision 1 FIGURE 1. Input Timing for RGB Interface FIGURE 2. Serial Data Valid FIGURE 3. Stop PClock Power Down FIGURE 4. Stop PClock Power Up 7 Print Date/Time: 2010/01/20 21:11:52 20172826 20172816 20172829 20172830 ...
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Functional Description The LM2512 is a Mobile Pixel Link (MPL) Serializer that se- rializes a 24-bit RGB plus three control signals (VS, HS, and DE) to two or three MPL MD lines plus the serial clock MC. The 24-bit RGB ...
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FIGURE 7. Three MD Lane MPL Interface SERIAL BUS TIMING Data valid is relative to both edges of a RGB transaction as shown in Figure 8. Data valid is specified as: Data Valid before Clock, Data Valid after Clock, and ...
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OFF PHASE In the OFF phase, MPL transmitters are turned off with zero current flowing on the MC and MDn lines. the transition of the MPL bus into the OFF phase MPL line is driven to a logical ...
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FIGURE 11. 24-bit to 18-bit Dithered Lane, RGB Transaction FIGURE 12. 24-bit to 18-bit Dithered Lane, RGB Transaction (NOTE MD1 and MD2) Serial Payload Parity Bit Odd Parity is calculated on the RGB bits, control (VS, ...
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LOOK UP TABLE OPTION AND SPI INTERFACE Three 256 X 8-bit SRAMs provide a Look Up Table for inde- pendent color correction. The LUT is disabled by default and also after a device PD* cycle. The PD* cycle can be ...
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FIGURE 13. LM2512 WRITE & READ to 3-signal SPI HOST FIGURE 14. LM2512 WRITE only to 4-signal SPI HOST 13 201728 Version 5 Revision 1 Print Date/Time: 2010/01/20 21:11:52 20172888 20172889 www.national.com ...
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LM2512 SPI Registers Name Addre Type ss Command 0x00 R/W Reserved 0x01 na (Note 15) Red RAM Address 0x02 R/W Red RAM Data 0x03 R/W Green RAM Address 0x04 R/W Green RAM Data 0x05 R/W Blue RAM Address 0x06 R/W ...
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SPI Timing 201728 Version 5 Revision 1 FIGURE 15. 16-bit SPI WRITE FIGURE 16. 16-bit SPI READ FIGURE 17. SPI PAGE WRITE 15 Print Date/Time: 2010/01/20 21:11:52 20172890 20172891 20172893 www.national.com ...
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Power Up Sequence The MPL Link must be powered up and enabled in a certain sequence for proper operation of the link and devices. The following list provides the recommended sequence: 1. Apply Power (See Power Supply Section) 2. PD* ...
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FPD95120 by issuing a Unlock command to the FPD95120 register 16’h which also de-se- lects / locks the LM2512 SPI. After the SPI commands are completed, the MPL_PD_N signal is driven High to arm the ...
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LM2512 Operation POWER SUPPLIES The V and V (MPL and PLL) must be connected to the DD DDA same potential between 1.6V and 2.0V. V logic interface and may be powered between 1.6V and 3. compatible with a ...
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The grounds are also useful for noise isolation and impedance control. PCB RECOMMENDATIONS General guidelines for the PCB design: • Floor plan, locate MPL SER near the connector to limit chance of cross talk to high speed serial signals. • ...
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Connection Diagram 49 UFBGA Package RGB SER Pinout SER 1 B1 SPI_SDA/ PCLK SSIO www.national.com TOP VIEW (not to scale RES1 ...
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Connection Diagram 40 LLP Package 201728 Version 5 Revision 1 TOP VIEW (not to scale) 21 Print Date/Time: 2010/01/20 21:11:52 20172896 www.national.com ...
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Physical Dimensions www.national.com inches (millimeters) unless otherwise noted 49L UFBGA, 0.5mm pitch Order Number LM2512SM NS Package Number SLH49A 40L LLP, 0.5mm pitch Order Number LM2512SN NS Package Number SNA40A 22 201728 Version 5 Revision 1 Print Date/Time: 2010/01/20 21:11:52 ...
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Notes 23 201728 Version 5 Revision 1 Print Date/Time: 2010/01/20 21:11:52 www.national.com ...
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... For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock and Timing www.national.com/timing Data Converters www.national.com/adc Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www ...