LM2512SM/NOPB National Semiconductor, LM2512SM/NOPB Datasheet - Page 14

• Manufacturer Part Number: LM2512SM/NOPB
• Description: IC SERIALIZER 24BIT RGB 49-UFBGA
• Manufacturer: National Semiconductor
• Series: LMr

Specifications of LM2512SM/NOPB

• Function: Serializer
• Data Rate: 468Mbps
• Input Type: LVCMOS
• Output Type: LVCMOS
• Number Of Inputs: 21
• Number Of Outputs: 3
• Voltage - Supply: 1.6 V ~ 3 V
• Operating Temperature: -30°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 49-UFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM2512SM

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Name
Command
Reserved
(Note
Red RAM Address
Red RAM Data
Green RAM Address
Green RAM Data
Blue RAM Address
Blue RAM Data
Dither Configuration1
(Note
Dither Configuration2
(Note
Lane Scale
(Note
Reserved
(Note
Device Select
(Unlock/Lock)
Reserved
(Note
LM2512 SPI Registers
Note 13: If a WRITE is done to a reserved bits, data should be all 0’s. If a READ is done to a reserved location, either 1’s or 0’s may be returned. Mask reserved
data bits.
Note 14: This register must be unlocked fist through bit 4 of register 0. This register is currently a write only register, read is not supported.
Note 15: DO NOT write to Reserved Registers.
15)
14)
14)
14)
15)
15)
Addre
0x0B-
0x17-
0x0A
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x15
0x16
0x7F
ss
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
na
na
na
W
201728 Version 5 Revision 1
Description
Bit 0 = LUT Enable
Bit 4 = Special Register Access
For access to Registers 0x08, 0x09, 0x0A, the Special Register Access bit must
be unlocked. Must write all 8 bits.
Reserved
Red Address
Red Data
Green Address
Green Data
Blue Address
Blue Data
Bit 0 - Dither Bypass
Bit 1 - DE INV
Bit 2 - VS INV
Bit 3 - Reserved
Bit 4 - Tempen0
Bit 5 - Tempen1
Bit 6 - Dith3 - Dither Amplitude
Bit 7 - Reserved
Dither Parameter
Reserved, Default value recommended.
Bit[2:0]
000’b = Reserved
010’b = 2 MD Lanes
100’b = 3 MD Lanes (Default)
all others= Reserved
Reserved
0xFF’h enables LM2512 SPI
All other values disables LM2512 SPI (0x00 to 0xFE)
Reserved
0’b = LUT Disabled, 1’b = LUT Enabled
0’b = SRA Locked, 1’b = SRA Unlocked
1’b = Bypass Dither, 0’b = Dither ON
1’b = Active Low DE, 0’b = Active High DE
Does not alter DE signal, dither block input only.
1’b = Active Low VS signal, 0’b = Active High VS signal.
Does not alter VS signal, dither block input only.
1’b = Transposed Dither Pattern,
0’b = Even and odd frames use same dither pattern
1’b = Temporal Dithering is Enabled, 0’b = Disabled
1’b = set to 3 bits, 0’b = set to 4 bits
Print Date/Time: 2010/01/20 21:11:52
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XX’h
00’h
00’h
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67’h
04’h
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