S1D13706F00A200 Epson, S1D13706F00A200 Datasheet - Page 113
![LCD Drivers (QVGA) 320x240 LCD Controller @ 8bpp](/photos/15/63/156392/tqfp-100_sml.jpg)
S1D13706F00A200
Manufacturer Part Number
S1D13706F00A200
Description
LCD Drivers (QVGA) 320x240 LCD Controller @ 8bpp
Manufacturer
Epson
Datasheet
1.S1D13706F00A200.pdf
(150 pages)
Specifications of S1D13706F00A200
Maximum Clock Frequency
33 MHz
Operating Supply Voltage
1.8 V to 2.2 V, 3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Package / Case
TQFP-100
Attached Touch Screen
No
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S1D13706F00A200
Manufacturer:
Epson Electronics America Inc-Semiconductor Div
Quantity:
10 000
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Epson Research and Development
Vancouver Design Center
bits 9-0
Hardware Functional Specification
Issue Date: 2008/12/16
PIP
REG[84h]
PIP
REG[85h]
+
+
Window X Start Position Register 0
Window X Start Position Register 1
7
7
6
6
Note
PIP
These bits determine the X start position of the PIP
panel. Due to the S1D13706 SwivelView feature, the X start position may not be a
horizontal position value (only true in 0° and 180° SwivelView). For further information
on defining the value of the X Start Position register, see Section 13, “Picture-in-Picture
Plus (PIP+)” on page 140.
The register is also incremented differently based on the SwivelView orientation. For 0°
and 180° SwivelView the X start position is incremented by x pixels where x is relative to
the current color depth.
For 90° and 270° SwivelView the X start position is incremented in 1 line increments.
Depending on the color depth, some of the higher bits in this register are unused because
the maximum horizontal display width is 1024 pixels.
1
(REG[71h] bit 4).
2
and at the next vertical non-display period.
+
These bits have no effect unless the PIP
The effect of REG[84h] through REG[91h] takes place only after REG[91h] is written
Window X Start Position Bits [9:0]
5
5
PIP
n/a
Table 8-11: 32-bit Address Increments for Color Depth
+
Window X Start Position Bits 7-0
4
4
Revision 10.3
Color Depth
16 bpp
1 bpp
2 bpp
4 bpp
8 bpp
3
3
+
Window Enable bit is set to 1
Pixel Increment (x)
+
window in relation to the origin of the
2
2
32
16
8
4
2
PIP
+
Window X Start Position
1
1
Bits 9-8
Read/Write
Read/Write
X31B-A-001-10
S1D13706
0
0
Page 113
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