S1D13706F00A200 Epson, S1D13706F00A200 Datasheet - Page 47

• Manufacturer Part Number: S1D13706F00A200
• Description: LCD Drivers (QVGA) 320x240 LCD Controller @ 8bpp
• Manufacturer: Epson

Specifications of S1D13706F00A200

• Maximum Clock Frequency: 33 MHz
• Operating Supply Voltage: 1.8 V to 2.2 V, 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Attached Touch Screen: No
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Epson Research and Development
Vancouver Design Center
1. t12 is the delay from when data is placed on the bus until the data is latched into the write buffer.
Hardware Functional Specification
Issue Date: 2008/12/16
Symbol
T
f
CLKO
CLKO
t5a
t5b
t5c
t5d
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t1
t2
t3
t4
t6
t7
t8
t9
Bus Clock frequency
Bus Clock period
Clock pulse width high
Clock pulse width low
A[16:1] setup 1st CLKO when CSX = 0 and either
UWE/LWE or OE = 0
A[16:1] hold from CSX rising edge
CSX asserted for MCLK = BCLK
CSX asserted for MCLK = BCLK ÷ 2
CSX asserted for MCLK = BCLK ÷ 3
CSX asserted for MCLK = BCLK ÷ 4
CSX setup to CLKO rising edge
CSX rising edge to CLKO rising edge
UWE/LWE falling edge to CLKO rising edge
UWE/LWE rising edge to CSX rising edge
OE falling edge to CLKO rising edge
OE hold from CSX rising edge
D[15:0] setup to 3rd CLKO when CSX,
UWE/LWE asserted (write cycle) (see note 1)
D[15:0] in hold from CSX rising edge (write cycle)
Falling edge of OE to D[15:0] driven (read cycle)
CLKO rising edge to D[15:0] output Hi-Z
(read cycle)
CSX falling edge to DTACK driven high
DTACK falling edge to D[15:0] valid (read cycle)
CSX high to DTACK high
CLKO rising edge to DTACK Hi-Z
Table 6-12: Motorola DragonBall Interface with DTACK Timing
Parameter
Revision 10.3
1/f
28.1
28.1
Min
CLKO
0
0
0
0
1
0
1
0
1
0
4
4
3
5
5
2.0V
MC68EZ328
Max
16
11
13
17
30
21
20
34
40
8
0
1/f
28.1
28.1
Min
CLKO
0
0
0
0
0
0
1
0
0
0
3
2
3
3
1
3.3V
Max
16
11
13
17
15
12
13
16
8
2
6
1/f
22.5
22.5
Min
CLKO
0
0
0
0
1
0
1
0
1
0
4
4
3
5
5
2.0V
MC68VZ328
Max
11
13
17
30
21
20
34
40
20
8
0
1/f
13.5
13.5
Min
CLKO
0
0
0
0
0
0
1
0
0
0
3
2
3
3
1
3.3V
X31B-A-001-10
Max
33
11
13
17
15
12
13
16
8
2
6
S1D13706
Page 47
T
T
T
T
MHz
Unit
CLKO
CLKO
CLKO
CLKO
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns