S1D13706F00A200 Epson, S1D13706F00A200 Datasheet - Page 4
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S1D13706F00A200
Manufacturer Part Number
S1D13706F00A200
Description
LCD Drivers (QVGA) 320x240 LCD Controller @ 8bpp
Manufacturer
Epson
Datasheet
1.S1D13706F00A200.pdf
(150 pages)
Specifications of S1D13706F00A200
Maximum Clock Frequency
33 MHz
Operating Supply Voltage
1.8 V to 2.2 V, 3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Package / Case
TQFP-100
Attached Touch Screen
No
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S1D13706F00A200
Manufacturer:
Epson Electronics America Inc-Semiconductor Div
Quantity:
10 000
Page 4
S1D13706
X31B-A-001-10
7
8
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
6.3
6.4
7.1
7.2
7.3
8.1
8.2
8.3
6.2.7
6.2.8
6.2.9
6.3.1
6.3.2
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
6.4.7
6.4.8
6.4.9
6.4.10 160x160 Sharp ‘Direct’ HR-TFT Panel Timing (e.g. LQ031B1DDxx) . . . . . . . 71
6.4.11 320x240 Sharp ‘Direct’ HR-TFT Panel Timing (e.g. LQ039Q2DS01) . . . . . . . . 75
6.4.12 160x240 Epson D-TFD Panel Timing (e.g. LF26SCR) . . . . . . . . . . . . . . . . 77
6.4.13 320x240 Epson D-TFD Panel Timing (e.g. LF37SQR) . . . . . . . . . . . . . . . . 80
7.1.1
7.1.2
7.1.3
7.1.4
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
LCD Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Display Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Clock Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Clocks versus Functions . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Register Mapping
Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Motorola REDCAP2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . 44
Motorola DragonBall Interface Timing with DTACK (e.g. MC68EZ328/MC68VZ328) 46
Motorola DragonBall Interface Timing w/o DTACK (e.g. MC68EZ328/MC68VZ328) 48
Passive/TFT Power-On Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Passive/TFT Power-Off Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Generic STN Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Single Monochrome 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . 55
Single Monochrome 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . 57
Single Color 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Single Color 8-Bit Panel Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . 61
Single Color 8-Bit Panel Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . 63
Single Color 16-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Generic TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
9/12/18-Bit TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
BCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
MCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
PCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
PWMCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Read-Only Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Clock Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Look-Up Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Panel Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Display Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Picture-in-Picture Plus (PIP+) Registers . . . . . . . . . . . . . . . . . . . . . . .111
Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Revision 10.3
Epson Research and Development
Hardware Functional Specification
Vancouver Design Center
Issue Date: 2008/12/16