M1AFS-EMBEDDED-KIT Actel, M1AFS-EMBEDDED-KIT Datasheet - Page 17

• Manufacturer Part Number: M1AFS-EMBEDDED-KIT
• Description: MCU, MPU & DSP Development Tools CortexM1-enabled Fusion Embedded Kit
• Manufacturer: Actel

Specifications of M1AFS-EMBEDDED-KIT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3 – Cortex-M1 Features
Programmer’s Model
Data Types
This section briefly outlines the main features of the Cortex-M1 processor. More detailed
information is available in the Cortex-M1 Technical Reference Manual.
The Cortex-M1 processor implements a subset of the Thumb-2 (ARMv7) architecture called ARMv6-M.
This includes all of the 16-bit Thumb-2 instructions and some of the 32-bit instructions. The processor
does not support ARM instructions.
The Thumb-2 (ARMv7) instruction set architecture (ISA) was developed by ARM for the Cortex family of
processors. Offering increased efficiency and performance, the Thumb-2 ISA differs from previous ARM
architectures in that it includes both 16- and 32-bit instructions. The previous 16-bit Thumb instruction set
and 32-bit ARM instruction set were separate and had to be executed from different modes within the
processor. The Thumb-2 ISA gives users all the advantages of the reduced code size of the 16-bit
Thumb instructions and the higher performance of the 32-bit ARM instructions. This is achieved in a
single ISA that can be executed
increasing the efficiency of the code as it executes and improving the performance and throughput of the
Cortex family of processors.
Processor Operating States
The Cortex-M1 processor has two operating states:
Processor Operating Modes
The Cortex-M1 processor supports two modes of operation:
Main Stack and Process Stack Access
Out of reset, all code uses the main stack with the processor in Thread mode.
configured with OS extensions present, a second (process) stack can be used in addition to
the main stack. The stack pointer (R13) becomes a banked register when OS extensions are
present.
Note:
The processor supports the following data types:
Note:
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Thumb state – This is normal execution, running the set of 16-bit, halfword-aligned Thumb and
Thumb-2 instructions; as well as the 32-bit BL, MRS, MSR, ISB, DSB, and DMB instructions.
Debug state – This is the state when halting debug
Thread mode – Entered on Reset, and can be re-entered as the result of an exception return
Handler mode – Entered as the result of an exception
32-bit words
16-bit halfwords
8-bit bytes
OS extensions are not supported on the majority of Actel M1 devices. OS extensions are supported
on the M1AFS1500 and M1A3PE1500 devices.
Unless otherwise stated, the core can access all regions of the memory map, including the code
region, with all data types. To support this, the system must support sub-word writes without
corrupting neighboring bytes in that word (i.e., individual byte enables for writes).
without requiring any context switching
R ev i si o n 1 2
within the processor,
If the processor is
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