M1AFS-EMBEDDED-KIT Actel, M1AFS-EMBEDDED-KIT Datasheet - Page 20

• Manufacturer Part Number: M1AFS-EMBEDDED-KIT
• Description: MCU, MPU & DSP Development Tools CortexM1-enabled Fusion Embedded Kit
• Manufacturer: Actel

Specifications of M1AFS-EMBEDDED-KIT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Cortex-M1 Features
Memory Map
20
Cortex-M1 has a defined memory map with the various processor interfaces addressed by different
memory map regions, as shown in
map with the exception of the reserved regions. The reserved regions are Execute Never (XN) and
instruction accesses are prevented by the processor hardware. The SRAM, Peripheral, External Device,
and Private Peripheral Bus regions in the memory map are also XN. Instructions can be executed from
the Code and External (not External Device) regions of the memory map.
Figure 3-2 • Cortex-M1 Memory Map
The processor views memory as a linear collection of bytes numbered in ascending order from 0.
For example:
•
Bytes 0
0xE00FFFFF
0xE00FF000
0xE0042000
0xE0041000
0xE0040000
0xE003FFFF
0xE000F000
0xE000ED00
0xE000E000
0xE0003000
0xE0002000
0xE0001000
0xE0000000
0x3FFFFFFF
0x20100000
0x20000000
0x1FFFFFFF
0x00100000
0x00000000
–
3 hold the first stored word
511MB
1 MB
511 MB
1 MB
Debug Control
ROM Table
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Note: TCMs shown are maximum size (1,024 kbytes).
NVIC
DW
BP
DTCM
ITCM
External
External
Figure
R ev i sio n 1 2
3-2. The processor can access all regions within the memory
Internal Private Peripheral Bus
External device
Peripheral
Reserved
External
SRAM
Code
0.5 GB
0.5 GB
0.5 GB
1 GB
1 GB
0xE0000000
0xDFFFFFFF
0xFFFFFFFF
0xE0100000
0xA0000000
0x9FFFFFFF
0x60000000
0x5FFFFFFF
0x40000000
0x3FFFFFFF
0x20000000
0x1FFFFFFF
0x00000000