M1AFS-EMBEDDED-KIT Actel, M1AFS-EMBEDDED-KIT Datasheet - Page 25

• Manufacturer Part Number: M1AFS-EMBEDDED-KIT
• Description: MCU, MPU & DSP Development Tools CortexM1-enabled Fusion Embedded Kit
• Manufacturer: Actel

Specifications of M1AFS-EMBEDDED-KIT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Clocking and Resets
For level interrupts, if the signal is not deasserted before the return from the interrupt routine, the
interrupt remains pending and re-activates. This is particularly useful for FIFO and buffer-based devices
because it ensures that they drain either by a single ISR or by repeated invocations, with no extra work.
This means that the device continues to assert the signal until the device is empty.
A pulse interrupt must be asserted for at least one HCLK cycle to enable the NVIC to latch the pending
bit.
A pulse interrupt can be reasserted during the ISR so that the interrupt can be pending and active at the
same time. If this occurs, the application design must ensure that a second pulse does not arrive before
the first pulse is activated. The second pulse cannot set the pending bit and would have no effect,
because the interrupt is already pending. However, if the interrupt is activated for at least one cycle, the
NVIC latches the pending bit. After the ISR activates, the pending bit is cleared. After the bit is cleared if
the interrupt is asserted again while it is activated, it can latch the pending bit again.
Note:
Clocks
HCLK is the main clock input and clocks the majority of the logic in the processor. When debug logic is
included the TCK input is used to clock logic in the debug access port. TCK is not functional when debug
logic is excluded. HCLK is also used for clocking some debug components when these are present.
Resets
Within the CortexM1Top level of hierarchy (see
in a number of reset signals and produces several reset outputs. The synchronization block ensures that
resets which may assert asynchronously are deasserted synchronous to the clock domain to which they
are relevant.
NSYSRESET is the main reset input. A power-on reset input, PORESETN, is functional when the core is
appropriately configured. Set the Reset to debug logic (DBGRESETn) configuration option to Driven
by PORESETN input if you have a power-on reset signal available in your system. Alternatively, you can
set this option to Driven by NSYSRESET input if no power-on reset is available. This latter setting is
less desirable because it means that if NSYSRESET (which is typically connected to a push-button
reset) is asserted during a debug session, then the debug connection will be lost as some of the debug
logic will be reset. If you have chosen not to include debug logic, the setting chosen for the Reset to
debug logic (DBGRESETn) option is of no consequence.
WDOGRES and WDOGRESn ports are provided to facilitate support of a watchdog type component
such as CoreWatchdog. WDOGRES is the "bark" signal from the watchdog and WDOGRESn is a reset
output to the watchdog.
When debug logic is included, the nTRST reset input is functional and is used to reset logic clocked by
TCK within the debug port.
The following paragraphs describe the reset outputs from the reset synchronization block and detail the
reset sources for each reset output.
HRESETn
HRESETn internally drives the SYSRESETn input of the processor core and is also an output from the
top level for use as a synchronized reset to other components in the design clocked by HCLK. HRESETn
is asserted whenever any of the following signals assert:
•
•
•
•
NSYSRESET (external push-button reset)
PORESETN (power-on reset signal)
SYSRESETREQ (reset request signal from processor core)
WDOGRES (bark signal from watchdog, if present in the processor subsystem)
The number of external interrupts is currently fixed at 1 in the majority of Actel M1 devices. A
processor configuration with 16 external interrupts is available for the M1AFS1500 and
M1A3PE1500 devices.
R ev i si o n 1 2
Figure 1-1 on page
9) a reset synchronization block takes
Cortex-M1 v3.1 Handbook
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