WM8731SEDS/V Wolfson Microelectronics, WM8731SEDS/V Datasheet - Page 53

• Manufacturer Part Number: WM8731SEDS/V
• Description: Audio CODECs Stereo Codec with H/P
• Manufacturer: Wolfson Microelectronics

Specifications of WM8731SEDS/V

• Interface Type: Serial (2-Wire or 3-Wire), I2S
• Resolution: 24 bit
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-28
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 2 ADC / 2 DAC
• Snr: 90 dB
• Thd Plus Noise: - 84 dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8731 / WM8731L
w
0000111
Digital Audio
Interface
Format
0001000
Sampling
Control
REGISTER
ADDRESS
1:0
3:2
4
5
6
7
0
1
5:2
6
7
BIT
FORMAT[1:0]
IWL[1:0]
LRP
LRSWAP
MS
BCLKINV
USB/
NORMAL
BOSR
SR[3:0]
CLKIDIV2
CLKODIV2
LABEL
10
10
0
0
0
0
0
0
0000
0
0
DEFAULT
Audio Data Format Select
11 = DSP Mode, frame sync + 2 data
packed words
10 = I
justified
01 = MSB-First, left justified
00 = MSB-First, right justified
Input Audio Data Bit Length Select
11 = 32 bits
10 = 24 bits
01 = 20 bits
00 = 16 bits
DACLRC phase control (in left, right
or I
1 = Right Channel DAC data when
DACLRC high
0 = Right Channel DAC data when
DACLRC low
(opposite phasing in I
or
DSP mode A/B select (in DSP mode
only)
1 = MSB is available on 2nd BCLK
rising edge after DACLRC rising edge
0 = MSB is available on 1st BCLK
rising edge after DACLRC rising edge
DAC Left Right Clock Swap
1 = Right Channel DAC Data Left
0 = Right Channel DAC Data Right
Master Slave Mode Control
1 = Enable Master Mode
0 = Enable Slave Mode
Bit Clock Invert
1 = Invert BCLK
0 = Don’t invert BCLK
Mode Select
1 = USB mode (250/272fs)
0 = Normal mode (256/384fs)
Base Over-Sampling Rate
USB Mode
0 = 250fs
1 = 272fs
ADC and DAC sample rate control;
See USB Mode and Normal Mode
Sample Rate sections for operation
Core Clock divider select
1 = Core Clock is MCLK divided by 2
0 = Core Clock is MCLK
CLKOUT divider select
1 = CLOCKOUT is Core Clock
divided by 2
0 = CLOCKOUT is Core Clock
2
S modes)
2
S Format, MSB-First left-1
DESCRIPTION
PD, Rev 4.8, April 2009
Normal Mode
0 = 256fs
1 = 384fs
2
S mode)
Production Data
53