ispPAC-CLK5610AV-01TN48C Lattice, ispPAC-CLK5610AV-01TN48C Datasheet - Page 22

• Manufacturer Part Number: ispPAC-CLK5610AV-01TN48C
• Description: Clock Drivers & Distribution ISP 0 Dlay Clck Gen w/Unv Fan-Out Buf I
• Manufacturer: Lattice
• Type: Zero Delay Programmable PLL Clock Generatorr

Specifications of ispPAC-CLK5610AV-01TN48C

• Max Input Freq: 400 MHz
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
pairs is not used, tie the unused pins REF+ and REF- to GND. In addition, if external feedback is not used, tied
FBVTT to GND.
One important point to note is that the termination supplies must have low impedance and be able to both source
and sink current without experiencing fluctuations. These requirements generally preclude the use of a resistive
divider network, which has an impedance comparable to the resistors used, or of commodity-type linear voltage
regulators, which can only source current. The best way to develop the necessary termination voltages is with a
regulator specifically designed for this purpose. Because SSTL and HSTL logic is commonly used for high-perfor-
mance memory busses, a suitable termination voltage supply is often already available in the system.
Figure 1-16. SSTL2, SSTL3, eHSTL, HSTL Receiver Configuration
Differential HSTL and SSTL
HSTL and SSTL are sometimes used in a differential form, especially for distributing clocks in high-speed memory
systems. Figure 1-17 shows how ispClock5600A reference input should be configured for accepting these stan-
dards. The major difference between differential and single-ended forms of these logic standards is that in the dif-
ferential case, the REFA- input is used as a signal input, not a reference level, and that both terminating resistors
are engaged and set to 50Ω. If one of the REF or FBK pairs is not used, tie the unused REF+ and REF- pins to
GND. If external feedback is not used, tie FBVTT to GND as well.
Figure 1-17. Differential HSTL/SSTL Receiver Configuration
VTT
VTT
+Signal In
Signal In
-Signal In
VREF IN
REFVTT
REFVTT
REFA+
REFA-
REFA+
REFA-
ispClock5600A
ispClock5600A
50
50
CLOSED
CLOSED
50
1-22
CLOSED
OPEN
Differential
Differential
Receiver
Receiver
ispClock5600A Family Data Sheet