ASD5010L500INT Arctic Silicon Devices, ASD5010L500INT Datasheet - Page 8

• Manufacturer Part Number: ASD5010L500INT
• Description: ADC (A/D Converters) A-D Conv, Dig Gain Dual 8 bit 500MSPS
• Manufacturer: Arctic Silicon Devices

Specifications of ASD5010L500INT

• Number Of Converters: 2
• Number Of Adc Inputs: 4
• Conversion Rate: 500 MSPs
• Resolution: 8 bit
• Snr: 49.5 dB
• Voltage Reference: 1 V
• Supply Voltage (max): 2 V
• Supply Voltage (min): 1.7 V
• Maximum Power Dissipation: 295 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-48
• Input Voltage: 1.8 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Preliminary Product Specification
Digital and Switching Specifications
AVDD=1.8V, DVDD=1.8V, OVDD=1.8V, RSDS output data levels, unless otherwise noted
ASD5010
Clock Inputs
DC
Compliance
V
V
V
V
C
Logic inputs (CMOS)
V
V
V
V
I
I
C
Data outputs
Compliance
V
V
V
Output coding
Timing
Characteristics
t
t
T
T
T
T
T
T
T
LVDS Output Timing
Characteristics
t
T
T
T
HI
LI
A
j
data
skew
SU
SLPCH
OVR
LATHSMQ
LATHSMD
LATHSMS
PROP
EDGE
CLKEDGE
CK,diff
CK,sine
CK,CMOS
CM,CK
HI
HI
LI
LI
OUT
OUT
CM
CK
I
Parameter
Duty Cycle
Differential input voltage swing
Differential input voltage swing, sine wave clock input
Voltage input range CMOS (CLKN connected to ground)
Input common mode voltage. Keep voltages within ground and
voltage of OVDD
Differential Input capacitance
High Level Input Voltage. V
High Level Input Voltage. V
Low Level Input Voltage. V
Low Level Input Voltage. V
High Level Input leakage Current
Low Level Input leakage Current
Input Capacitance
Differential output voltage, LVDS
Differential output voltage, RSDS
Output common mode voltage
Default/optional
Aperture delay
Aperture jitter, One bit set to '1' in jitter_ctrl<7:0>
Timing skew between ADC channels
Start up time from Power Down Mode and Deep Sleep Mode to
Active Mode in µs. See section "Clock Frequency" for details.
Start up time from Sleep Channel Mode to Active Mode
Out of range recovery time
Pipeline delay, Quad Channel Mode
Pipeline delay, Dual Channel Mode
Pipeline delay, Single Channel Mode
LCLK to data delay time (excluding programmable phase shift)
Clock propagation delay.
LVDS bit-clock duty-cycle
Frame clock cycle-to-cycle jitter
Data rise- and fall time 20% to 80%
Clock rise- and fall time 20% to 80%
OVDD
OVDD
Description
OVDD
OVDD
≥ 3.0V
= 1.7V – 3.0V
≥ 3.0V
= 1.7V – 3.0V
rev 2.0, 2010.11.08
Page 8 of 35
0.8 ·V
6*T
+/-200
+/-800
Offset Binary/ 2's complement
Min
+2.2
0.3
45
45
2
0
0
LVDS
CMOS, LVDS, LVPECL
OVDD
LVDS / RSDS
7*T
V
+3.5
Typ
350
150
160
128
OVDD
1.2
1.5
2.5
0.7
0.7
15
32
64
50
3
3
1
LVDS
V
0.2 ·V
OVDD
7*T
+/-10
+/-10
Max
+5.0
0.8
2.5
55
55
LVDS
OVDD
-0.3 V
Confidential
% high
mVpp
mVpp
pF
V
V
V
V
µA
µA
pF
mV
mV
V
ns
fsrms
psrms
µs
µs
clock
cycles
clock
cycles
clock
cycles
clock
cycles
ps
ns
% LCLK
cycle
% LCLK
cycle
ns
ns
Unit