MAX1441GUP/V+ Maxim Integrated Products, MAX1441GUP/V+ Datasheet - Page 38

• Manufacturer Part Number: MAX1441GUP/V+
• Description: Touch Screen Converters & Controllers PROXIMITY SENSR el Proximity and Tou
• Manufacturer: Maxim Integrated Products

Specifications of MAX1441GUP/V+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Automotive, Two-Channel Proximity and
Touch Sensor
The device implements an I/O port that is slightly differ-
ent from those found in other MAXQ products.
The I/O port is still governed by the PI0, PO0, and PD0
registers.
When a PD0 register is cleared to 0, the port pin is oper-
ating as input and the pin is high impedance. The PI
register contains the input value. PI is read only. PI may
not always immediately equal PO due to capacitance at
the output.
When a PD0 bit is set to 1, the output is enabled and
the port pin output data corresponds to the PO value. In
addition, OUT1 and OUT2 can ONLY be used as open-
drain outputs. To use OUT1 and OUT2, clear PO bit to 0
and drive PD bit with inverted data.
When used as inputs, do not leave the port unconnect-
ed. Program unused port pins as outputs.
The external interrupt flag (EIF) is set to 1 when either a
rising or falling edge is detected on a port pin regardless
of its PD0 value. An interrupt is generated if it is enabled
(EIE = 1).
At power-up, weak pullups are enabled on pin P0.[4:0].
To disable a pullup, clear the associated bit in the PO0
register.
The external interrupts are asynchronous.
In the discussion that follows, priority only has mean-
ing when two peripherals are both configured to drive
outputs at the same time. Then one of the named
peripheral’s output has priority over the other, thus
making the other’s output disabled. Note that the lower
priority peripheral can still be running and trying to
output value onto the pad. However, since it has lower
priority, its output is not driven onto the pad. For inputs,
all peripherals have equal priority—even though the
inputs may not be desirable. This means that if two input
peripherals sharing the same pin are enabled, both of
them receive the same input concurrently.
When a pin operates as input (whether it is a GPIO or
special-function input), its behavior is governed by PO0
and PD0. Anytime a pin behaves as an output (because
one of its special functions is configured as output), PO0
and PD0 are no longer used.
Port 0 supports the following functions: JTAG and GPIO.
All special functions have priority over GPIO.
38
Peripheral Prioritization
I/O Ports
The following apply when port pins are multiplexed with
the JTAG function:
• The Special-Function Enable (SF Enable) signal for
• The Special-Function Input, when disabled, should be
• The TDO Special-Function Enable requires not only
Following each system reset, the device automatically
activates the utility ROM at 8000h. The reset vector in
the utility ROM determines whether the program flow is to
start in the user mode or the ROM bootstrap mode. The
factor that determines which program is executed is the
System Programming Enable (SPE) bit in the ICDF reg-
ister. The SPE can be set/cleared with the debug mode
command using the TAP interface.
The device supports various modes of system opera-
tions. Normally, the device is running in user mode to
support user applications. The ROM bootstrap load-
er mode is used for initializing memory and system
configuration. The debug mode is intended to provide
real-time in-circuit debugging/emulation. The debug mode
is supported through a test access port (TAP) and the TAP
controller, which is compatible to the JTAG standard.
The TAP and the TAP controller are enabled after any
reset, but remain inactive until a valid command is
entered into the instruction register so as not to disrupt
normal user-mode operation. If the TAP is not used,
or the TAP interface pins are needed to serve another
purpose, the TAP can be disabled by clearing the TAP
enable (TAP) bit located in the SC system register.
Depending upon the mode desired, the instruction regis-
ter should be loaded with the associated "debug" or "in-
system programming" instruction. The method for loading
the instruction register is described in the subsequent
sections. These modes can be established anytime the
digital supply voltage is above the POR threshold (e.g.,
during system reset both are acceptable).
these JTAG pins must be active during reset so
that the JTAG port is accessible during this time. SF
enable is controlled by the TAP register bit, which is
set to 1 on all resets.
gated high for TMS. This disables the JTAG interface
and forces the TAP into the Test-Logic-Reset state if
the TCK pin has been toggled for more than five times.
that TAP = 1, but also that the TAP be in the Shift-IR or
Shift-DR state. The debug engine already produces a
control signal (TDONZ) to denote when the TAP is in
a shift state.
System Operating Modes
JTAG Pin Special Function