M4A5-128/64-12VNI Lattice, M4A5-128/64-12VNI Datasheet - Page 35

• Manufacturer Part Number: M4A5-128/64-12VNI
• Description: CPLD - Complex Programmable Logic Devices HI PERF E2CMOS PLD
• Manufacturer: Lattice

Specifications of M4A5-128/64-12VNI

• Number Of Macrocells: 128
• Number Of Product Terms Per Macro: 20
• Maximum Operating Frequency: 83.3 MHz
• Delay Time: 5 ns
• Number Of Programmable I/os: 160
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Package / Case: TQFP-100
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Circuit Type: Electrically Erasable
• Logic Function: Programmable
• Logic Type: CMOS
• Package Type: TQFP-100
• Special Features: High Speed, In-System Programmability
• Temperature, Operating, Range: -40 to +85 °C
• Voltage, Supply: 3 to 3.6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

BLOCK DIAGRAM - M4A3-512/160, M4A3-512/192, M4A3-512/256
Detail A
Block C
Block F
Block G
Block K
Block N
Block J
16
16
16
16
24
24
24
24
16
16
16
16
and Logic Allocator
and Logic Allocator
and Logic Allocator
and Logic Allocator
AND Logic Array
Output Switch
AND Logic Array
Output Switch
Output Switch
AND Logic Array
Output Switch
AND Logic Array
Macrocells
Macrocells
Macrocells
Macrocells
I/O Cells
I/O Cells
I/O Cells
I/O Cells
72 X 90
Matrix
72 X 90
Matrix
Block O
Matrix
72 X 90
Matrix
72 X 90
Block B
16
16
16
16
8
8
8
8
8
36
8
36
36
16
16
8
36
16
16
8
8
8
8
8
4
4
4
4
4
4
4
4
4
4
4
4
Block D
Block E
Block H
Block M
Block L
Block I
16
16
16
16
24
24
24
24
16
16
16
16
and Logic Allocator
and Logic Allocator
and Logic Allocator
and Logic Allocator
AND Logic Array
Output Switch
AND Logic Array
Output Switch
Output Switch
AND Logic Array
Output Switch
AND Logic Array
Macrocells
Macrocells
Macrocells
Macrocells
I/O Cells
I/O Cells
I/O Cells
I/O Cells
Matrix
72 X 90
Matrix
Matrix
72 X 90
Matrix
Block A
72 X 90
72 X 90
Block P
16
16
16
16
8
8
8
8
8
36
36
16
16
8
8
36
36
16
16
8
ispMACH 4A Family
8
8
8
8
4
4
4
4
4
4
4
4
4
4
4
4
Repeat Detail A
Repeat Detail A
CLK0–CLK3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
8
8
8
8
and Logic Allocator
and Logic Allocator
and Logic Allocator
and Logic Allocator
AND Logic Array
AND Logic Array
AND Logic Array
AND Logic Array
Output Switch
Output Switch
Output Switch
Output Switch
Block PX
I/O Cells
I/O Cells
Block AX
Macrocells
72 X 90
I/O Cells
Macrocells
72 X 90
I/O Cells
72 X 90
Macrocells
72 X 90
Macrocells
16
16
36
36
16
16
16
16
36
36
16
16
8
Matrix
8
8
Matrix
8
Matrix
Matrix
8
8
8
8
16
16
16
16
24
24
24
24
16
16
16
16
Block MX
Block LX
Block IX
Block HX
Block EX
Block DX
4
4
4
4
4
4
4
4
4
4
4
4
8
8
8
8
and Logic Allocator
and Logic Allocator
and Logic Allocator
and Logic Allocator
AND Logic Array
AND Logic Array
AND Logic Array
AND Logic Array
Output Switch
Output Switch
Output Switch
Output Switch
Block BX
Block OX
Macrocells
I/O Cells
Macrocells
I/O Cells
I/O Cells
Macrocells
72 X 90
72 X 90
I/O Cells
Macrocells
72 X 90
72 X 90
16
16
36
36
16
16
16
16
36
36
16
16
Matrix
8
Matrix
8
8
Matrix
8
Matrix
8
8
8
8
16
16
16
16
24
24
24
24
16
16
16
16
Block NX
Block KX
Block JX
Block GX
Block FX
Block CX
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